Interconnection structures in a semiconductor device and methods of manufacturing the same

Abstract

Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

What is claimed is: 
     
         1 . A method of fabricating interconnection structures of a semiconductor device, the method comprising:
 forming a first insulation layer on a semiconductor substrate;   forming a mold layer having trenches on the first insulation layer;   forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches;   forming second metal lines that fill the trenches;   forming upper protection layers on the second metal lines;   removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines; and   forming a second insulation layer in the gaps and on the upper protection layers,   wherein the second insulation layer is formed to include gaps between the second metal lines.   
     
     
         2 . The method of  claim 1 , wherein forming the second metal lines includes forming a copper layer that fills the trenches. 
     
     
         3 . The method of  claim 2 , wherein the first metal silicide layer is formed to include a cobalt silicide layer or a tantalum silicide layer. 
     
     
         4 . The method of  claim 1 , wherein each of the upper protection layers is formed to include a cobalt layer or a cobalt alloy layer. 
     
     
         5 . The method of  claim 4 , wherein the cobalt alloy layer is formed to include a cobalt-tungsten-phosphorus (CoWP) alloy layer, a cobalt-tungsten (CoW) alloy layer, a cobalt-tungsten-boron (CoWB) alloy layer, or a cobalt-tungsten-phosphorus-boron (CoWPB) alloy layer. 
     
     
         6 . The method of  claim 1 , wherein the second insulation layer is deposited such that overhangs are formed on upper corners of the second metal lines to provide voids in the gaps between second metal lines. 
     
     
         7 . The method of  claim 6 , wherein the second insulation layer is formed of a silicon oxide layer or a silicon nitride layer using a plasma enhanced chemical vapor deposition (PECVD) process. 
     
     
         8 . The method of  claim 7 , wherein the second metal lines are formed to have sloped sidewall profiles such that an upper width of each of the second metal lines is greater than a lower width thereof. 
     
     
         9 . The method of  claim 8 , wherein the trenches are formed to have sloped sidewall profiles such that an upper width of each of the trenches is greater than a lower width thereof. 
     
     
         10 . A method of fabricating interconnection structures of a semiconductor device, the method comprising:
 forming a first insulation layer on a semiconductor substrate;   forming a silicon mold layer having trenches on the first insulation layer;   forming a first metal layer covering sidewalls of the trenches;   reacting the first metal layer with the silicon mold layer to form first metal silicide layers acting as sidewall protection layers;   forming second metal lines that fill the trenches;   forming upper protection layers on the second metal lines;   removing the silicon mold layer after formation of the upper protection layers to provide gaps between second metal lines; and   forming a second insulation layer in the gaps and on the upper protection layers,   wherein the second insulation layer is formed to include air gaps between the second metal lines.   
     
     
         11 . The method of  claim 10 , further comprising forming contact plugs that penetrate the first insulation layer to connect the semiconductor substrate to the second metal lines prior to formation of the silicon mold layer. 
     
     
         12 . The method of  claim 10 , wherein forming the silicon mold layer includes:
 depositing a silicon layer on the first insulation layer; and   patterning the silicon mold layer to form the trenches.   
     
     
         13 . The method of  claim 12 , wherein forming the first metal layer includes forming a cobalt containing layer that directly contacts sidewalls of the trenches. 
     
     
         14 . The method of  claim 13 , wherein the cobalt containing layer is formed by depositing a cobalt layer. 
     
     
         15 . The method of  claim 14 , wherein the cobalt containing layer is formed to extend onto bottom surfaces of the trenches. 
     
     
         16 . The method of  claim 15 , wherein forming the sidewall protection layers includes annealing the cobalt containing layer and the silicon mold layer to form cobalt silicide layers corresponding to the first metal silicide layers that cover the sidewalls of the trenches, and
 wherein portions of the cobalt containing layer on the bottom surfaces of the trenches remain without any reaction during formation of the cobalt silicide layers, thereby functioning as bottom barrier layers.   
     
     
         17 . The method of  claim 16 , wherein annealing the cobalt containing layer and the silicon mold layer is performed using a rapid thermal annealing (RTA) process at a temperature of about 450° C. to about 800° C. 
     
     
         18 . The method of  claim 16 , wherein removing the silicon mold layer is performed using a wet etching process that employs a mixture of nitric acid (HNO 3 ), hyfrofluoric acid (HF), and de-ionized water or a chemical solution including ammonium hydroxide (NH 4 OH) as an etchant. 
     
     
         19 . The method of  claim 10 , wherein forming the second metal lines includes forming copper layers that fill the trenches. 
     
     
         20 . The method of  claim 19 , wherein forming the upper protection layers includes selectively depositing a cobalt layer or a cobalt-tungsten-phosphorus (CoWP) alloy layer on the copper layers using a chemical vapor deposition (CVD) process. 
     
     
         21 . A method of fabricating interconnection structures of a semiconductor device, the method comprising:
 forming a first insulation layer on a semiconductor substrate;   forming a mold layer having trenches on the first insulation layer;   forming sidewall spacers including a silicon layer on sidewalls of the trenches;   forming a first metal layer covering the sidewall spacers;   reacting the first metal layer with the sidewall spacers to form first metal silicide layers acting as sidewall protection layers;   forming second metal lines that fill the trenches;   forming upper protection layers on the second metal lines;   removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines; and   forming a second insulation layer in the gaps and on the upper protection layers,   wherein the second insulation layer is formed to include air gaps between the second metal lines.   
     
     
         22 . The method of  claim 21 , wherein forming the first metal layer includes forming a cobalt containing layer that directly contacts the sidewall spacers. 
     
     
         23 . The method of  claim 22 , wherein the cobalt contacting layer is formed to extend onto bottom surfaces of the trenches. 
     
     
         24 . The method of  claim 22 ,
 wherein forming the sidewall protection layers includes annealing the cobalt containing layer and the sidewall spacers to form cobalt silicide layers corresponding to the first metal silicide layers that cover the sidewalls of the trenches, and   wherein portions of the cobalt containing layer on the bottom surfaces of the trenches remain without any reaction during formation of the cobalt silicide layers, thereby functioning as bottom barrier layers.   
     
     
         25 . An interconnection structure of a semiconductor device, the interconnection structure comprising:
 a first insulation layer on a semiconductor substrate;   second metal lines on the first insulation layer opposite to the semiconductor substrate;   first metal silicide layers disposed on sidewalls of the second metal lines to act as sidewall protection layers;   upper protection layers on top surfaces of the second metal lines; and   a second insulation layer including air gaps between the second metal lines and extending onto the upper protection layers.   
     
     
         26 . The interconnection structure of  claim 25 , further comprising contact plugs that penetrate the first insulation layer to connect the semiconductor substrate to the second metal lines. 
     
     
         27 . The interconnection structure of  claim 25 , further comprising bottom barrier layers between the first insulation layer and the second metal lines,
 wherein each of the bottom barrier layers includes a cobalt containing layer.   
     
     
         28 . The interconnection structure of  claim 27 , wherein the cobalt containing layer includes a cobalt layer. 
     
     
         29 . The interconnection structure of  claim 25 , wherein each of the second metal lines includes a copper layer. 
     
     
         30 . The interconnection structure of  claim 25 , wherein each of the first metal silicide layers includes a cobalt silicide layer or a tantalum silicide layer. 
     
     
         31 . The interconnection structure of  claim 25 , wherein each of the upper protection layers includes a cobalt layer or a cobalt alloy layer. 
     
     
         32 . The interconnection structure of  claim 25 , wherein the second insulation layer includes a silicon oxide layer or a silicon nitride layer. 
     
     
         33 . The interconnection structure of  claim 25 , wherein an upper width of each of the second metal lines is greater than a lower width thereof. 
     
     
         34 . An interconnection structure of a semiconductor device, the interconnection structure comprising:
 a first insulation layer on a semiconductor substrate;   copper lines on the first insulation layer opposite to the semiconductor substrate;   cobalt silicide layers disposed on sidewalls of the copper lines to act as sidewall protection layers;   upper protection layers on top surfaces of the copper lines; and   a second insulation layer including air gaps between the copper lines and extending onto the upper protection layers.   
     
     
         35 . The interconnection structure of  claim 34 , further comprising bottom barrier layers between the first insulation layer and the copper lines,
 wherein each of the bottom barrier layers includes a cobalt containing layer.   
     
     
         36 . The interconnection structure of  claim 34 , wherein the copper lines are bit lines.