Edge selection techniques for correcting clock duty cycle

Abstract

Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

1 . A circuit for generating a clock signal, comprising:
 a multiplexer circuit to selectively output one of a plurality of input clock signals; and   an edge-triggered flip-flop circuit comprising a clock signal port, a data signal port, and an output port, wherein the clock signal port is connected to an output of the multiplexer circuit,   wherein the data signal port receives a data signal, and wherein the output port of the edge-triggered flip-flop circuit is connected to a select control port of the multiplexer circuit,   wherein the edge-triggered flip-flop circuit detects a transitioning edge of an input clock signal that is selectively output from the multiplexer circuit, and in response to said detection, samples a logic, level of the received data signal, and generates a transition of an output clock signal at the output port,   wherein the multiplexer circuit selectively outputs one of the plurality of input clock signals to the clock signal port of the edge-triggered flip-flop circuit, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop circuit, which is input to the select control port of the multiplexer circuit, and   wherein the plurality of input clock signals are clock signals with distorted duty cycles, and wherein the circuit corrects the duty cycles of the input clock signals by using the multiplexer circuit to select transitioning edges of the input clock signals that are substantially equally spaced in time and by using the selected transitioning edges to trigger the edge-triggered flip-flop circuit to generate an output clock signal at the output port which is substantially free of duty cycle distortion.   
     
     
         2 . The circuit of  claim 1 , wherein the edge-triggered flip-flop circuit detects a rising edge of the input clock signal selectively output from the multiplexer circuit. 
     
     
         3 . The circuit of  claim 1 , wherein the edge-triggered flip-flop circuit detects a falling edge of the input clock signal selectively output from the multiplexer circuit. 
     
     
         4 . The circuit of  claim 1 , wherein the multiplexer circuit is a 2:1 multiplexer. 
     
     
         5 . The circuit of  claim 1 , further comprising an output clock phase definition circuit that generates the data signal which is input to the data input port of the edge-triggered flip-flop circuit, wherein the data signal is a dock signal having a frequency equal to a frequency of the input dock signals. 
     
     
         6 . The circuit of  claim 5 , wherein the output clock phase definition circuit comprises a delay circuit. 
     
     
         7 . The circuit of  claim 1 , further comprising an inverter circuit having an input connected to the output port of the edge-triggered flip-flop circuit, and having an output connected to the data signal port of the edge-triggered flip-flop circuit. 
     
     
         8 . The circuit of  claim 1 , wherein the edge-triggered flip-flop circuit is an asynchronously resettable edge-triggered flip-flop circuit. 
     
     
         9 . (canceled) 
     
     
         10 . A semiconductor integrated circuit chip comprising, an integrated circuit, the integrated circuit comprising a clock generation circuit, wherein the clock generation circuit comprises:
 a multiplexer circuit to selectively output one of a plurality of input clock signals; and   an edge-triggered flip-flop circuit comprising a clock signal port, a data signal port, and an output port, wherein the clock signal port is connected to an output of the multiplexer circuit,   wherein the data signal port receives a data signal, and wherein the output port of the edge-triggered flip-flop circuit is connected to a select control port of the multiplexer circuit,   wherein the edge-triggered flip-flop circuit detects a transitioning edge of an input clock signal that is selectively output from the multiplexer circuit, and in response to said detection, samples a logic level of the received data signal, and generates a transition of an output clock signal at the output port,   wherein the multiplexer circuit selectively outputs one of the plurality of input clock signals to the clock signal port of the edge-triggered flip-flop circuit, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop circuit , which is input to the select control port of the multiplexer circuit, and   wherein the plurality of input clock signals are clock signals with distorted duty cycles, and wherein the circuit corrects the duty cycles of the input clock signals by using the multiplexer circuit to select transitioning edges of the input clock signals that are substantially equally spaced in time, and by using the selected transitioning edges to trigger the edge-triggered flip-flop circuit to generate an out lilt clock signal at the out ion which is substantially free of duty cycle distortion.   
     
     
         11 . The semiconductor integrated circuit chip of  claim 10 , wherein the edge-triggered flip-flop circuit detects a rising edge of the input clock signal selectively output from the multiplexer circuit. 
     
     
         12 . The semiconductor integrated circuit chip of  claim 10 , wherein the edge-triggered flip-flop circuit detects a falling edge of the input clock signal selectively output from the multiplexer circuit. 
     
     
         13 . The semiconductor integrated circuit chip of  claim 10 , wherein the multiplexer circuit is a 2:1 multiplexer. 
     
     
         14 . The semiconductor integrated circuit chip of  claim 10 , wherein the clock generation circuit further comprises an output clock phase definition circuit that generates the data signal which is input to the data input port of the edge-triggered flip-flop circuit, wherein the data signal is a clock signal having a frequency equal to a frequency of the input clock signals. 
     
     
         15 . The semiconductor integrated circuit chip of  claim 14 , wherein the output clock phase definition circuit comprises a delay circuit. 
     
     
         16 . The semiconductor integrated circuit chip of  claim 10 , wherein the clock generation circuit further comprises an inverter circuit having an input connected to the output port of the edge-triggered flip-flop circuit, and having an output connected to the data signal port of the edge-triggered flip-flop circuit. 
     
     
         17 . The semiconductor integrated circuit chip of  claim 10 , wherein the edge-triggered flip-flop circuit is an asynchronously resettable edge-triggered flip-flop circuit. 
     
     
         18 . (canceled) 
     
     
         19 . A circuit for generating a clock signal, comprising:
 a multiplexer circuit to selectively output one of a plurality of input clock signals: and   an edge-triggered flip-flop circuit comprising a clock signal port, a data signal port, and an output port, wherein the clock signal port is connected to an output of the multiplexer circuit,   wherein the data signal port receives a data signal, and wherein the output port of the edge-triggered flip-flop circuit is connected to a select control port of the multiplexer circuit,   wherein the edge-triggered flip-flop circuit detects a transitioning edge of an input clock. signal that is selectively output from the multiplexer circuit, and in response to said detection, samples a logic level of the received data signal, and generates a transition of an output clock signal at the output port, and   wherein the multiplexer circuit selectively outputs one of the plurality of input clock signals to the dock signal port of the edge-triggered flip-flop circuit, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop circuit, which is input to the select control port of the multiplexer circuit.