US2013212408A1PendingUtilityA1

Regulating a clock frequency of a peripheral

42
Individually held — no corporate assignee on recordPriority: Feb 9, 2012Filed: Feb 9, 2012Published: Aug 15, 2013
Est. expiryFeb 9, 2032(~5.5 yrs left)· nominal 20-yr term from priority
Inventors:Kenneth W. Fernald
G06F 1/324Y02D10/00
42
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Claims

Abstract

A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The processor has a power state. The method also includes regulating a clock frequency of the peripheral, where this regulation is based at least in part on the power state of the processor.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method comprising:
 in a first power state of a processor, using the processor to communicate with a peripheral; and   regulating a clock frequency of the peripheral based at least in part on a power state of the processor.   
     
     
         2 . The method of  claim 1 , wherein regulating the clock frequency further comprises changing the clock frequency of the peripheral. 
     
     
         3 . The method of  claim 1 , wherein
 the processor is adapted to transition between a first power state to a second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state; and   regulating the clock frequency further comprises changing the clock frequency from a first frequency to a second frequency greater than the first frequency.   
     
     
         4 . The method of  claim 1 , wherein
 the processor is adapted to transition between a first power state and a second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state; and   regulating the clock frequency further comprises changing the clock frequency from a first frequency to a second frequency less than the first frequency.   
     
     
         5 . The method of  claim 1 , further comprising:
 using the peripheral to trigger transition of the processor from a first power state to a second power state,   wherein the processor is adapted to transition from the first power state to the second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state.   
     
     
         6 . The method of  claim 5 , wherein the triggering comprises performing one of communicating a wakeup signal and communicating an interrupt signal. 
     
     
         7 . The method of  claim 6 , further comprising:
 using the peripheral to trigger transition of the processor from a first power state to a second power state in response to the peripheral transitioning from a third power state to a fourth power state,   wherein the processor is adapted to transition between the first power state and the second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state; and the peripheral is adapted to transition between the third power state and the fourth power state, the fourth power state being associated with a greater power consumption than a power consumption associated with the third power state.   
     
     
         8 . The method of  claim 7 , further comprising transitioning the peripheral from the third power state to the fourth power state in response to the peripheral transmitting or receiving data. 
     
     
         9 . An apparatus comprising:
 a peripheral;   a processor adapted to communicate with the peripheral,   wherein the peripheral is adapted to regulate a clock frequency of the peripheral based at least in part on a power state of the processor.   
     
     
         10 . The apparatus of  claim 9 , wherein the peripheral is adapted to change the clock frequency of the peripheral to prepare the peripheral for communication with the processor. 
     
     
         11 . The apparatus of  claim 9 , wherein
 the processor is adapted to transition between a first power state and a second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state; and   the peripheral is adapted to change the clock frequency from a first frequency to a second frequency greater than the first frequency.   
     
     
         12 . The apparatus of  claim 11 , wherein the peripheral is adapted to alert the processor to transition the processor from the first power state to the second power state. 
     
     
         13 . The apparatus of  claim 9 , wherein the peripheral comprises a controller adapted to select a clock signal for the peripheral. 
     
     
         14 . The apparatus of  claim 9 , wherein the peripheral comprises one of the following: a universal synchronous/asynchronous receiver/transmitter (USART) component, a universal asynchronous receiver/transmitter (UART) component, a serial peripheral interface (SPI) component and an inter-integrated circuit (I 2 C) component. 
     
     
         15 . The apparatus of  claim 9 , wherein
 the processor is adapted to transition between a first power state and a second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state; and   the peripheral is adapted to change the clock frequency from a first frequency to a second frequency less than the first frequency.   
     
     
         16 . The apparatus of  claim 9 , wherein
 the processor is adapted to transition between a first power state and a second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state; and   the peripheral is further adapted to:
 transition between a third power state and a fourth power state, the fourth power state being associated with a greater power consumption than a power consumption associated with the third power state; and 
 trigger transition of the processor from the first power state to the second power state. 
   
     
     
         17 . An apparatus comprising:
 an integrated circuit comprising a processor and a peripheral, wherein:   the processor is adapted to communicate with the peripheral and the peripheral is adapted to regulate a clock frequency of the peripheral based at least in part on a power state of the processor.   
     
     
         18 . The apparatus of  claim 17 , wherein the peripheral is adapted to change the clock frequency of the peripheral to prepare the peripheral for communication with the processor. 
     
     
         19 . The apparatus of  claim 17 , wherein
 the processor is adapted to transition between a first power state and a second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state; and   the peripheral is adapted to change the clock frequency of the peripheral from a first frequency to a second frequency greater than the first frequency.   
     
     
         20 . The apparatus of  claim 17 , wherein
 the processor is adapted to transition between a first power state and a second power state, the second power state being associated with a greater power consumption than a power consumption associated with the first power state; and   the peripheral is adapted to change the clock frequency of the peripheral from a first frequency to a second frequency less than the first frequency.

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