Media Action Script Acceleration Apparatus

Abstract

Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

It is claimed: 
     
         1 . An apparatus for processing an action script for visual display of a graphical image, the apparatus comprising:
 at least one memory circuit to store a plurality of operational codes and a plurality of control words; and   a plurality of processors to parse the action script into a plurality of descriptive elements and corresponding data, to extract data from the action script and to store the extracted data in the at least one memory circuit as the plurality of control words having the extracted data in predetermined fields, wherein the plurality of descriptive elements are a plurality of tags or bytecodes; to convert the plurality of descriptive elements of the action script into the plurality of operational codes; to decode each operational code of the plurality of operational codes to generate a plurality of communication signals; and to perform a selected operation in response to a selected communication signal of the plurality of communication signals using the extracted data stored in the at least one memory circuit to generate pixel data for the graphical image.   
     
     
         2 . The apparatus of  claim 1 , wherein the plurality of communication signals are selected from the group consisting of: control signals, instructions, hardware-level instructions, hardware-level microcode, messages, control words, status words, and combinations thereof. 
     
     
         3 . The apparatus of  claim 1 , wherein the plurality of processors further are to decode a descriptive element to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script. 
     
     
         4 . The apparatus of  claim 1 , wherein the plurality of processors further are to determine a type of descriptive element; to determine or select a number of bits to parse parameter; and to control shifting of a number of bits designated by the number of bits to parse parameter. 
     
     
         5 . The apparatus of  claim 1 , wherein at least one processor of the plurality of processors further comprises:
 at least one arithmetic logic unit; and   at least one floating point circuit.   
     
     
         6 . The apparatus of  claim 5 , further comprising:
 a configurable interconnect coupled to the at least one arithmetic logic unit and to the at least one floating point execution unit.   
     
     
         7 . The apparatus of  claim 1 , wherein at least one processor of the plurality of processors is coupled to the first memory through at least one connection selected from the group consisting of: an interconnection network, a configurable interconnect, a packet-based interconnect, a circuit-switched interconnect, a crosspoint switch, a serial bus, a parallel bus, a network, and combinations thereof. 
     
     
         8 . The apparatus of  claim 1 , wherein the plurality of processors further are to match a plurality of line or curve segments of a boundary of the graphical image and to determine a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image, and to apply a fill style to generate pixel data for an area of the graphical image. 
     
     
         9 . The apparatus of  claim 1 , further comprising:
 a frame buffer;   wherein the plurality of processors further are to separate the action script from other data and to perform hypertext transfer protocol (“HTTP”) for reception of a data file and to generate pixel data for hypertext markup language (“HTML”) or extensible markup language (“XML”) data of the data file; to transfer the pixel data for the graphical image to the frame buffer; and to transfer the pixel data for the HTML or XML data to the frame buffer.   
     
     
         10 . The apparatus of  claim 1 , wherein the plurality of processors further comprise a plurality of processor cores selected from the group consisting of: central processing (CPU) cores, graphics processing (GPU) cores, and combinations thereof; and wherein the plurality of processor cores are embodied in a single integrated circuit or a plurality of integrated circuits. 
     
     
         11 . An apparatus for processing an action script for visual display of a graphical image, the apparatus comprising:
 at least one memory circuit to store a plurality of operational codes and a plurality of control words;   a configurable interconnect coupled to the memory circuit; and   a plurality of processors to parse the action script into a plurality of descriptive elements and corresponding data, to extract data from the action script and to store the extracted data in the at least one memory circuit as the plurality of control words having the extracted data in predetermined fields, wherein the plurality of descriptive elements are a plurality of tags or bytecodes; to convert the plurality of descriptive elements of the action script into the plurality of operational codes; to decode each operational code of the plurality of operational codes to generate a plurality of control signals or instructions; and to perform a selected operation in response to a selected control signal or instruction of the plurality of control signals or instructions using the extracted data stored in the at least one memory circuit to generate pixel data for the graphical image; and wherein at least one processor core of the plurality of processors is coupled to the first memory through the configurable interconnect.   
     
     
         12 . The apparatus of  claim 11 , wherein the plurality of processors further are to convert the action script directly to the plurality of operational codes by performing a deterministic function on each descriptive element of the plurality of descriptive elements to generate a corresponding result and to use the result to determine a corresponding operational code of the plurality of operational codes. 
     
     
         13 . The apparatus of  claim 11 , further comprising:
 a frame buffer;   wherein the plurality of processors further are to separate the action script from other data and to perform hypertext transfer protocol (“HTTP”) for reception of a data file and to generate pixel data for hypertext markup language (“HTML”) or extensible markup language (“XML”) data of the data file; to transfer the pixel data for the graphical image to the frame buffer; and to transfer the pixel data for the HTML or XML data to the frame buffer.   
     
     
         14 . The apparatus of  claim 11 , wherein the plurality of processors further are to separate the action script from other data and to decode each operational code of the plurality of operational codes to generate corresponding control signals or instructions of the plurality of control signals or instructions to control performance of a selected operation, of a plurality of operations, corresponding to a selected operational code of the plurality of operational codes. 
     
     
         15 . The apparatus of  claim 14 , wherein at least one processor of the plurality of processors further comprises a floating point circuit and an arithmetic logic unit, and wherein the plurality of processors further are to generate a first corresponding control signal or instruction to enable the floating point circuit to perform the selected operation and to decode an operational code of the plurality of operational codes to generate a corresponding plurality of control signals or instructions to select a calculation result generated by the arithmetic logic unit. 
     
     
         16 . The apparatus of  claim 11 , wherein the plurality of processors further are to decode a descriptive element to determine a corresponding parsing operational code of the plurality of operational codes to control the parsing of the action script. 
     
     
         17 . The apparatus of  claim 11 , wherein the plurality of processors further are to match a plurality of line or curve segments of a boundary of the graphical image and to determine a sequential ordering of the plurality of line or curve segments to form boundary coordinates of the graphical image. 
     
     
         18 . The apparatus of  claim 17 , wherein the plurality of processors further are to apply a fill style to generate pixel data for an area of the graphical image. 
     
     
         19 . The apparatus of  claim 18 , wherein the plurality of processors further are to apply a line style by forming a second graphical image from a boundary of the graphical image, and wherein the ninth circuitry is further configured to apply a fill style to the second graphical image to generate pixel data for the line style. 
     
     
         20 . A handheld apparatus for processing an action script for visual display of a graphical image, the apparatus comprising:
 a network input and output interface configured to receive a data file;   a user input and output interface;   a frame buffer to store the pixel data;   at least one memory circuit to store a plurality of operational codes and a plurality of control words; and   a plurality of processors or processor cores to parse the action script into a plurality of descriptive elements and corresponding data, to extract data from the action script and to store the extracted data in the at least one memory circuit as the plurality of control words having the extracted data in predetermined fields, wherein the plurality of descriptive elements are a plurality of tags or bytecodes; to convert the plurality of descriptive elements of the action script into the plurality of operational codes; to decode each operational code of the plurality of operational codes to generate a plurality of communication signals; and to perform a selected operation in response to a selected communication signal of the plurality of communication signals using the extracted data stored in the at least one memory circuit to generate pixel data for the graphical image; and to generate second pixel data for hypertext markup language (“HTML”) or extensible markup language (“XML”) data of the data file and to transfer the second pixel data to the frame buffer.