Multi-interface compatible bus over a common physical connection

Abstract

A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

1 - 28 . (canceled) 
     
     
         29 . A system comprising:
 a first circuit board to:
 identify whether a second circuit board, communicating with the first circuit board, is designed to communicate synchronously or asynchronously over a communication bus that includes a plurality of communication lines; and 
 selectively communicate with the second circuit board using a first communication scheme when the second circuit board is designed to communicate synchronously and using a second communication scheme when the second circuit board is designed to communicate synchronously,
 the first communication scheme including using all of the plurality of communication lines of the communication bus and a multiplexer operating based on a first clock signal, and 
 the second communication scheme including using fewer than all of the plurality of communication lines of the communication bus and the multiplexer operating based on a second clock signal. 
 
   
     
     
         30 . The system of  claim 29 , where, when identifying whether the second circuit board is designed to communicate synchronously or asynchronously, the first circuit board is to identify whether the second circuit board is designed to communicate synchronously or asynchronously based on an initial communication pattern used by the second circuit board. 
     
     
         31 . The system of  claim 29 , where, when the second circuit board is designed to communicate asynchronously, the first circuit board is to receive, from the second circuit board, redundant clock inputs and data. 
     
     
         32 . The system of  claim 29 , where the first circuit board is further to:
 communicate with the second circuit board using a first rate when the second circuit board is designed to communicate asynchronously; and   communicate with the second circuit board using a second rate when the second circuit board is designed to communicate synchronously,
 the first rate being faster than the second rate. 
   
     
     
         33 . The system of  claim 29 , where the first circuit board is further to:
 configure the multiplexer to receive the first clock signal from an oscillator when the second circuit board is designed to communicate synchronously.   
     
     
         34 . The system of  claim 29 , where the first circuit board is further to:
 configure the multiplexer to receive the second clock signal from a phased lock loop when the second circuit board is designed to communicate synchronously.   
     
     
         35 . The system of  claim 29 , where the first circuit board is connected to the second circuit board via a midplane. 
     
     
         36 . A method comprising:
 identifying, by a first circuit board, whether a second circuit board, communicating with the first circuit board, is designed to communicate synchronously or asynchronously over a communication bus that includes a plurality of communication lines; and   selectively communicating, by the first circuit board, with the second circuit board using a first communication scheme when the second circuit board is designed to communicate synchronously and using a second communication scheme when the second circuit board is designed to communicate asynchronously,
 the first communication scheme including using all of the plurality of communication lines of the communication bus and a multiplexer operating based on a first clock signal, and 
 the second communication scheme including using fewer than all of the plurality of communication lines of the communication bus and the multiplexer operating based on a second clock signal. 
   
     
     
         37 . The method of  claim 36 , where identifying whether the second circuit board is designed to communicate synchronously or asynchronously comprising:
 identifying whether the second circuit board is designed to communicate synchronously or asynchronously based on an initial communication pattern used by the second circuit board.   
     
     
         38 . The method of  claim 36 , further comprising:
 receiving, from the second circuit board, redundant clock inputs and data when the second circuit board is designed to communicate asynchronously.   
     
     
         39 . The method of  claim 36 , further comprising:
 communicating, by the first circuit board, with the second circuit board using a first rate when the second circuit board is designed to communicate asynchronously; and   communicating, by the first circuit board, with the second circuit board using a second rate when the second circuit board is designed to communicate synchronously,
 the first rate being faster than the second rate. 
   
     
     
         40 . The method of  claim 36 , further comprising:
 configuring the multiplexer to receive the first clock signal from an oscillator when the second circuit board is designed to communicate synchronously.   
     
     
         41 . The method of  claim 36 , further comprising:
 configuring the multiplexer to receive the second clock signal from a phased lock loop when the second circuit board is designed to communicate synchronously.   
     
     
         42 . The method of  claim 36 , where the first circuit board is connected to the second circuit board via a midplane. 
     
     
         43 . A network device comprising:
 a first card capable of communicating, asynchronously or synchronously, with a second card inserted into the network device through a bus formed by a plurality of communication lines, the first card to:
 identify, when the second card is inserted into the network device, whether the second card is designed to communicate synchronously or asynchronously; and 
 selectively communicate with the second board using a first communication scheme when the second card is designed to communicate synchronously and using a second communication scheme when the second card is designed to communicate asynchronously,
 the first communication scheme including using all of the plurality of communication lines of the bus, and 
 the second communication scheme including using fewer than all of the plurality of communication lines of the bus. 
 
   
     
     
         44 . The network device of  claim 43 , where, when identifying whether the second card is designed to communicate synchronously or asynchronously, the first card is to identify whether the second card is designed to communicate synchronously or asynchronously based on an initial communication pattern used by the second card. 
     
     
         45 . The network device of  claim 43 , where, when the second card is designed to communicate asynchronously, the first card is to receive, from the second card, redundant clock inputs and data. 
     
     
         46 . The network device of  claim 43 , where the first card is further to:
 communicate with the second card using a first rate when the second card is designed to communicate asynchronously; and   communicate with the second card using a second rate when the second card is designed to communicate synchronously,
 the first rate being faster than the second rate. 
   
     
     
         47 . The network device of  claim 43 , where the first card includes a multiplexer, an oscillator, and a phased lock loop, and where the first card is to:
 configure the multiplexer to receive a first clock signal from the oscillator when the second card is designed to communicate synchronously, and   configure the multiplexer to receive a second clock signal from the phased lock loop when the second card is designed to communicate synchronously,
 the first clock signal being different than the second clock signal. 
   
     
     
         48 . The network device of  claim 43 , further comprising a midplane to connect the first card to the second card.