US2013223800A1PendingUtilityA1
Surface mount (smt) connector for vcsel and photodiode arrays
Est. expiryOct 22, 2024(expired)· nominal 20-yr term from priority
Inventors:Edris M. Mohammed
H10F 55/25G02B 6/4257G02B 6/4249G02B 6/428G02B 6/4292G02B 6/43H01L 31/167
63
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Claims
Abstract
Self alignment of Optoelectronic (OE) chips, such as photodiode (PD) modules and vertical cavity surface emitting laser (VCSEL) modules, to external waveguides or fiber arrays may be realized by packaging the OE chips directly in the fiber optic connector.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . An apparatus, comprising:
at least a first optical connector; and an optoelectronic module housed within the first optical connector.
2 . The apparatus as recited in claim 1 , wherein the optoelectronic component comprises a vertical cavity surface emitting laser (VCSEL).
3 . The apparatus as recited in claim 1 wherein the optoelectronic component comprises a photo-diode (PD).
4 . The apparatus as recited in claim 1 further comprising:
solder bumps on a surface of the optical connector to flip-chip mount the connector to a board.
5 . The apparatus as recited in claim 1 further comprising:
a second optical connector;
a second optoelectronic module housed within the second optical connector; and
a fiber optic connecting cord connecting the first optical connector and the second optical connector.
6 . An optical connector, comprising:
a substrate; a first set of solder bumps on the substrate a second set of solder bumps at a bottom edge of the substrate electrically connected to the first set of solder bumps; an optoelectronic device flip-chip bonded to the first set of solder bumps; an optical connector housing encasing the substrate; and solder bumps on a bottom of the optical connector electrically connected to second set of solder bumps.
7 . The optical connector as recited in claim 6 , further comprising:
alignment holes within the optical connector housing to mate with alignment pins from a complimentary optical connector.
8 . The optical connector as recited in claim 6 wherein the substrate comprises glass.
9 . The optical connector as recited in claim 6 wherein the optoelectronic component comprises a vertical cavity surface emitting laser (VCSEL) array module.
10 . The optical connector as recited in claim 6 wherein the optoelectronic component comprises a photodiode (PD) array module.
11 . The optical connector as recited in claim 6 wherein the optical connector housing comprises a mechanically transferable (MT) connector.
12 . A system comprising:
a laser packaged within a first optical connector housing mounted to a first electronic chip; a photodiode packaged within a second optical connector housing mounted to a second electronic chip; and an optical fiber cord having a complimentary optical connectors at either end to mate with the first optical connector housing and the second optical connector housing to optically connect the first electronic chip to the second electronic chip.
13 . The system as recited in claim 12 , further comprising:
transmitter circuitry electrically connected to the laser; and receiver circuitry electrically connected to the photodiode.
14 . The system as recited in claim 13 , wherein the first electronic chip and the second electronic chip comprise part of a central processing unit (CPU) package.
15 . The system as recited in claim 13 wherein the first electronic chip resides in a peripheral module.
16 . The system as recited in claim 13 wherein the second electronic chip resides in a peripheral module.
17 . The system as recited in claim 16 , wherein in the peripheral module comprises a memory.
18 . A method, comprising:
housing a laser in a first surface mount (SMT) connector; flip-chip bonding the first SMT connector to a first electronic chip; housing a photodiode (PD) in a second SMT connector; flip-chip bonding the second SMT connector to a second electronic chip; optically connecting the first electronic chip with the second electronic chip via an optical cord plugged into the first SMT connector and the second SMT connector.
19 . The method as recited in claim 18 wherein the first electronic chip and the second electronic chip reside in a central processing unit (CPU) package.
20 . The method as recite in claim 18 wherein the first electronic chip wherein the first electronic chip resides in an electronic package and the second electronic chip resides in a peripheral device.
21 . The method as recited in claim 18 wherein the second electronic chip resides in an electronic package and the second electronic chip resides in a peripheral device.Cited by (0)
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