Resilient Integrated Circuit Architecture

Abstract

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

It is claimed: 
     
         1 . An integrated circuit comprising:
 a first plurality of composite circuit elements and a second plurality of composite circuit elements, each composite circuit element of the first and second pluralities of composite circuit elements comprising an element interface and a circuit element of a plurality of circuit element types, wherein each element interface comprises:
 a register to store at least one context; 
 an element controller coupled to the circuit element; 
 a first plurality of queues to store input data for the circuit element; and 
 a second plurality of queues to store output data from the circuit element; 
   a third plurality of queues to transfer a data word between the first plurality of composite circuit elements and the second plurality of composite circuit elements; and   a first full interconnect bus coupling every queue of the second plurality of queues of the first plurality of composite circuit elements to every queue of the first plurality of queues of the first plurality of composite circuit elements and to every queue of the third plurality of queues.   
     
     
         2 . The integrated circuit of  claim 1 , further comprising:
 a processor.   
     
     
         3 . The integrated circuit of  claim 2 , wherein a first composite circuit element has a configurable, programmable or assignable first data link through the first full interconnect bus to a second composite circuit element for performance of a first data operation and a configurable, programmable or assignable second data link through a queue of the third plurality of queues to a third composite circuit element for performance of a second data operation. 
     
     
         4 . The integrated circuit of  claim 3 , wherein the first data link and the second data link are configured, programmed or assigned in a binding process, the binding process occurring substantially during run-time, or at run-time, or before run-time, or any combination thereof. 
     
     
         5 . The integrated circuit of  claim 3 , wherein the processor is to configure, program or assign a function to the third composite circuit element and provide for the second data link in response to an unavailability of the second composite circuit element. 
     
     
         6 . The integrated circuit of  claim 5 , wherein the second composite circuit element is unavailable due to a detected fault. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the plurality of circuit element types is selected from the group consisting of: a configurable element type, a memory element type, a communication element type, a processor element type, a non-configurable element type, and combinations thereof. 
     
     
         8 . The integrated circuit of  claim 1 , wherein the register of each element interface further is to store a plurality of contexts, each context of the plurality of contexts specifying a configuration of a plurality of configurations of the circuit element, and specifying either or both a data input source or a data output destination. 
     
     
         9 . The integrated circuit of  claim 8 , wherein the element controller further is to store in the register a current state of a partial execution of a first context of the plurality of contexts, execute a second context of the plurality of contexts, and retrieve the current state and resume execution of the first context. 
     
     
         10 . The integrated circuit of  claim 8 , wherein the element controller further is to direct an execution of a context of the plurality of contexts by the circuit element when all designated input queues of the first plurality of queues for the context have input data, when all designated output queues of the second plurality of queues for the context have room to accept data, and when a status bit corresponding to the context is set for execution. 
     
     
         11 . The integrated circuit of  claim 10 , wherein the element controller further is to arbitrate among a plurality of contexts which are ready for execution and to select a corresponding context for execution as a result of the arbitration. 
     
     
         12 . The integrated circuit of  claim 1 , further comprising:
 a second full interconnect bus coupling every queue of the second plurality of queues of the second plurality of composite circuit elements to every queue of the first plurality of queues of the second plurality of composite circuit elements and to every queue of the third plurality of queues.   
     
     
         13 . The integrated circuit of  claim 12 , wherein the second plurality of composite circuit elements is adjacent to the first plurality of composite circuit elements, and wherein the second full interconnect bus is coupled to the first full interconnect bus through at least one queue of the third plurality of queues. 
     
     
         14 . The integrated circuit of  claim 1 , wherein at least one circuit element of the plurality of circuit element types is a sequential, reduced instruction set processor circuit. 
     
     
         15 . The integrated circuit of  claim 1 , wherein any function of any composite circuit element of the first and second pluralities of composite circuit elements using input data from any input queue of the first plurality of queues and providing output data to an output queue of the second plurality of queues is performed within a single clock cycle. 
     
     
         16 . The integrated circuit of  claim 1 , wherein any data transfer from an output queue of the second plurality of queues to any input queue of the first plurality of queues or to any queue of the third plurality of queues, over the first full interconnect bus, is performed within a single clock cycle, and wherein any data transfer from a queue of the third plurality of queues to any input queue of the first plurality of queues, over the first full interconnect bus, is performed within a single clock cycle. 
     
     
         17 . The integrated circuit of  claim 1 , wherein the plurality of circuit element types comprise at least two circuit element types selected from the group consisting of: a configurable arithmetic logic unit, a configurable multiplier, a configurable bit reordering element, a configurable multiply and accumulate element, a configurable Galois multiplier, a configurable barrel shifter, a configurable look-up table, a programmable controller, a configurable controller, a processor, a configurable plurality of arithmetic logic units; and combinations thereof. 
     
     
         18 . An integrated circuit comprising:
 at least one processor core;   a first plurality of composite circuit elements and a second plurality of composite circuit elements, each composite circuit element of the first and second pluralities of composite circuit elements comprising an element interface and a circuit element of a plurality of circuit element types, wherein each element interface comprises:
 a register to store at least one context; 
 an element controller coupled to the circuit element; 
 a first plurality of queues to store input data for the circuit element; and 
 a second plurality of queues to store output data from the circuit element; 
   a third plurality of queues to transfer a data word between the first plurality of composite circuit elements and the second plurality of composite circuit elements;   a first full interconnect bus coupling every queue of the second plurality of queues of the first plurality of composite circuit elements to every queue of the first plurality of queues of the first plurality of composite circuit elements and to every queue of the third plurality of queues; and   a second full interconnect bus coupling every queue of the second plurality of queues of the second plurality of composite circuit elements to every queue of the first plurality of queues of the second plurality of composite circuit elements and to every queue of the third plurality of queues.   
     
     
         19 . The integrated circuit of  claim 18 , wherein a first composite circuit element has a configurable, programmable or assignable first data link through the first full interconnect bus to a second composite circuit element for performance of a first data operation and a configurable, programmable or assignable second data link through a queue of the third plurality of queues to a third composite circuit element for performance of a second data operation, and wherein the first data link and the second data link are configured, programmed or assigned in a binding process, the binding process occurring substantially during run-time, or at run-time, or before run-time, or any combination thereof. 
     
     
         20 . The integrated circuit of  claim 18 , wherein the plurality of circuit element types is selected from the group consisting of: a configurable element type, a memory element type, a communication element type, a processor element type, a non-configurable element type, and combinations thereof. 
     
     
         21 . The integrated circuit of  claim 18 , wherein the register of each element interface further is to store a plurality of contexts, each context of the plurality of contexts specifying a configuration of a plurality of configurations of the circuit element, and specifying either or both a data input source or a data output destination. 
     
     
         22 . The integrated circuit of  claim 21 , wherein the element controller further is to store in the register a current state of a partial execution of a first context of the plurality of contexts, execute a second context of the plurality of contexts, and retrieve the current state and resume execution of the first context. 
     
     
         23 . The integrated circuit of  claim 21 , wherein the element controller further is to direct an execution of a context of the plurality of contexts by the circuit element when all designated input queues of the first plurality of queues for the context have input data, when all designated output queues of the second plurality of queues for the context have room to accept data, and when a status bit corresponding to the context is set for execution. 
     
     
         24 . The integrated circuit of  claim 23 , wherein the element controller further is to arbitrate among a plurality of contexts which are ready for execution and to select a corresponding context for execution as a result of the arbitration. 
     
     
         25 . The integrated circuit of  claim 18 , wherein the second plurality of composite circuit elements is adjacent to the first plurality of composite circuit elements, and wherein the second full interconnect bus is coupled to the first full interconnect bus through at least one queue of the third plurality of queues. 
     
     
         26 . The integrated circuit of  claim 18 , wherein any function of any composite circuit element of the first and second pluralities of composite circuit elements using input data from any input queue of the first plurality of queues and providing output data to an output queue of the second plurality of queues is performed within a single clock cycle; wherein any data transfer from an output queue of the second plurality of queues to any input queue of the first plurality of queues or to any queue of the third plurality of queues, over the first full interconnect bus, is performed within a single clock cycle, and wherein any data transfer from a queue of the third plurality of queues to any input queue of the first plurality of queues, over the first full interconnect bus, is performed within a single clock cycle. 
     
     
         27 . The integrated circuit of  claim 18 , wherein the plurality of circuit element types comprise at least two circuit element types selected from the group consisting of: a configurable arithmetic logic unit, a configurable multiplier, a configurable bit reordering element, a configurable multiply and accumulate element, a configurable Galois multiplier, a configurable barrel shifter, a configurable look-up table, a programmable controller, a configurable controller, a processor, a configurable plurality of arithmetic logic units; and combinations thereof. 
     
     
         28 . An integrated circuit comprising:
 a plurality of processor cores;   a first plurality of composite circuit elements and a second plurality of composite circuit elements, each composite circuit element of the first and second pluralities of composite circuit elements comprising an element interface and a circuit element of a plurality of circuit element types, wherein each element interface comprises:
 a register to store a plurality of contexts, each context of the plurality of contexts specifying a configuration of a plurality of configurations of the circuit element, and specifying either or both a data input source or a data output destination; 
 an element controller coupled to the circuit element; 
 a first plurality of queues to store input data for the circuit element; and 
 a second plurality of queues to store output data from the circuit element; 
   a configuration bus coupled to the register of each element interface;   a third plurality of queues to transfer a data word between the first plurality of composite circuit elements and the second plurality of composite circuit elements;   a first full interconnect bus coupling every queue of the second plurality of queues of the first plurality of composite circuit elements to every queue of the first plurality of queues of the first plurality of composite circuit elements and to every queue of the third plurality of queues; and   a second full interconnect bus coupling every queue of the second plurality of queues of the second plurality of composite circuit elements to every queue of the first plurality of queues of the second plurality of composite circuit elements and to every queue of the third plurality of queues, wherein the second full interconnect bus is coupled to the first full interconnect bus through at least one queue of the third plurality of queues.   
     
     
         29 . The integrated circuit of  claim 28 , wherein the element controller further is to direct an execution of a context of the plurality of contexts by the circuit element when all designated input queues of the first plurality of queues for the context have input data, when all designated output queues of the second plurality of queues for the context have room to accept data, and when a status bit corresponding to the context is set for execution. 
     
     
         30 . The integrated circuit of  claim 18 , wherein any function of any composite circuit element of the first and second pluralities of composite circuit elements using input data from any input queue of the first plurality of queues and providing output data to an output queue of the second plurality of queues is performed within a single clock cycle; wherein any data transfer from an output queue of the second plurality of queues to any input queue of the first plurality of queues or to any queue of the third plurality of queues, over the first full interconnect bus, is performed within a single clock cycle, and wherein any data transfer from a queue of the third plurality of queues to any input queue of the first plurality of queues, over the first full interconnect bus, is performed within a single clock cycle. 
     
     
         31 . The integrated circuit of  claim 28 , wherein the plurality of circuit element types comprise at least two circuit element types selected from the group consisting of: a configurable arithmetic logic unit, a configurable multiplier, a configurable bit reordering element, a configurable multiply and accumulate element, a configurable Galois multiplier, a configurable barrel shifter, a configurable look-up table, a programmable controller, a configurable controller, a processor, a configurable plurality of arithmetic logic units; and combinations thereof.