Nonvolatile semiconductor storage device having encrypting arithmetic device

Abstract

According to one embodiment, a nonvolatile semiconductor storage device includes an encrypting circuit for operating in a predetermined encrypting system, a memory cell array preliminarily storing complementary data to be used in the operation, and a page buffer having a first region for storing the data being read out from the memory cell array, and a second region used when executing the operation.

What is claimed is: 
     
         1 . A nonvolatile semiconductor storage device comprising:
 an encrypting circuit for executing an operation of a predetermined encrypting system,   a memory cell array preliminarily storing complementary data to be used in the operation,   a page buffer comprising a first region for storing the data being read out from the memory cell array, and a second region used at the time of execution of the operation,   a register for storing the data from the first region, and supplying the stored data into the second region,   an inspection circuit for judging presence or absence of error in the data when storing the data into the register, and storing the data into the register when the data is judged to be free from error,   a control circuit for controlling to read out the data from the memory cell array into the first region, and controlling to read out the data from the first region into the second region, and   an address control circuit for designating an address of the page buffer or the memory cell array, based on a signal supplied from the control circuit,   wherein the control circuit controls the address control circuit, and supplies the data from the first region into the second region, and   when the inspection circuit detects an error in the data, it is notified to the address control circuit, and   the address control circuit receives the notice, and designates other address in which data of same contents as the data in the page buffer is stored, and thereby   the inspection circuit judges presence or absence of error in the data in the other address.   
     
     
         2 . A nonvolatile semiconductor storage device comprising:
 an encrypting circuit for executing an operation of a predetermined encrypting system,   a memory cell array preliminarily storing data to be used in the operation,   a page buffer comprising a first region for storing the data being read out from the memory cell array, and a second region used at the time of execution of the operation, and   a register for storing the data from the first region, and supplying the stored data into the second region.   
     
     
         3 . The device according to  claim 2 , further comprising:
 an inspection circuit for judging presence or absence of error in the data when storing the data into the register, and storing the data into the register when the data is judged to be free from error.   
     
     
         4 . The device according to  claim 3 , further comprising:
 a control circuit for controlling to read out the data from the memory cell array into the first region, and controlling to read out the data from the first region into the second region, and   an address control circuit for designating an address of the page buffer or the memory cell array, based on a signal supplied from the control circuit,   wherein the control circuit controls the address control circuit, and supplies the data from the first region into the second region, and   when the inspection circuit detects an error in the data, it is notified to the address control circuit, and   the address control circuit receives the notice, and designates other address in which data of same contents as the data in the page buffer is stored, and thereby   the inspection circuit judges presence or absence of error in the data in the other address.   
     
     
         5 . The device according to  claim 4 , wherein the control circuit supplies the data stored in the register into the second region prior to the operation. 
     
     
         6 . The device according to  claim 5 , wherein the control circuit performs the operation by using the data when the data is stored in the second region. 
     
     
         7 . The device according to  claim 6 , wherein the control circuit judges presence or absence of error in the data about all addresses in which data of same contents as the data is stored, and stores the data in the register when the data is judged to contain an error. 
     
     
         8 . The device according to  claim 7 , wherein the encrypting circuit performs the operation by using the data judged to contain an error. 
     
     
         9 . The device according to  claim 8 , wherein the encrypting circuit is same in the time required for the operation by using the data judged to contain an error, and in the time required for the operation by using the data judged to be free or error. 
     
     
         10 . The device according to  claim 9 , wherein the operation result contains information about presence or absence of error in the data. 
     
     
         11 . The device according to  claim 2 , wherein the operation result is stored in the second region. 
     
     
         12 . The device according to  claim 2 , wherein the data includes two types, slot key and media key. 
     
     
         13 . The device according to  claim 12 , wherein when both the slot key and the media key are stored in the second region, the encrypting circuit performs the operation by using the slot key and the media key. 
     
     
         14 . The device according to  claim 12 , wherein the control circuit causes the inspection circuit to judge presence or absence of error in the slot key, and to judge presence or absence of error in the slot key. 
     
     
         15 . The device according to  claim 12 , wherein the register has the storage region at least equal in size to the data length of the slot key. 
     
     
         16 . The device according to  claim 2 , wherein the data is complementary data. 
     
     
         17 . The device according to  claim 2 , further comprising:
 an operation unit provided between the memory cell array and the page buffer,   wherein the operation unit performs a part of the operation executed by the encrypting circuit.   
     
     
         18 . A nonvolatile semiconductor storage device comprising:
 an encrypting circuit for executing an operation of a predetermined encrypting system,   a memory cell array preliminarily storing data to be used in the operation, and   a page buffer for performing the operation.