Multi layer chip capacitor, and method and apparatus for manufacturing the same

Abstract

A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer including adjusting and setting a distance between a single shadow mask installed to a mask set to be rotated and revolved and having a plurality of slits, positioning a dielectric layer deposition source to be perpendicular to the single shadow mask and a conductor layer deposition source to be oblique to the single shadow mask, and forming the dielectric layer and the conductor layer in the vacuum deposition while controlling the mask set to move along the X-, Y-, and Z-axes (the X-axis is the width direction, the Y-axis is the longitudinal direction, and the Z-axis is the height direction).

What is claimed: 
     
         1 . A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:
 adjusting and setting a distance between a single shadow mask installed to a mask set to be rotated and revolved and having a plurality of slits;   positioning a dielectric layer deposition source to be perpendicular to the single shadow mask and a conductor layer deposition source to be oblique to the single shadow mask; and   forming the dielectric layer and the conductor layer in the vacuum deposition while controlling the mask set to move along the X-, Y-, and Z-axes (the X-axis is the width direction, the Y-axis is the longitudinal direction, and the Z-axis is the height direction).   
     
     
         2 . The method of manufacturing a multi-layer chip capacitor according to  claim 1 , further comprising forming a thermally decomposable releasing layer on the substrate before the setting. 
     
     
         3 . The method of manufacturing a multi-layer chip capacitor according to  claim 1 , further comprising controlling the mask set to move in the height direction to prevent a deposition layer formed on the substrate from being damaged by the shadow mask after the formation of the deposition layer and to be spaced apart from the substrate, and to be positioned in the horizontal direction defined as the width direction and the longitudinal direction. 
     
     
         4 . A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:
 forming slit patterns for forming desired deposition layers by moving upper and lower mask sets which respectively include shadow masks having a plurality of slits and face each other; and   forming the dielectric layer and the conductor layer by evaporating evaporated particles from respective deposition sources to pass through the slit patterns and to be deposited on the substrate.   
     
     
         5 . The method of manufacturing a multi-layer chip capacitor according to  claim 4 , further comprising moving the mask sets, in which the shadow masks are mounted, in the height direction based on a layer growth rates of the conductor layer and the dielectric layer during the deposition of the conductor layer and the dielectric layer. 
     
     
         6 . The method of manufacturing a multi-layer chip capacitor according to  claim 4 , further comprising repeating a control of the shadow masks to be separated from the substrate during the deposition of the conductor layer and the dielectric layer and of precisely adjusting the positions of the separated shadow masks upwardly based on growth rates of the deposited layers every predetermined time period. 
     
     
         7 . The method of manufacturing a multi-layer chip capacitor according to  claim 4 , further comprising controlling the mask sets to move in the height direction to prevent deposition layers formed on the substrate from being damaged by the shadow masks after the formation of the deposition layers and to be spaced apart from the substrate, and to be positioned in the horizontal direction defined as the width direction and the longitudinal direction. 
     
     
         8 . A multi-layer chip capacitor manufactured by the method of manufacturing the multi-layer chip capacitor according to  claim 4 . 
     
     
         9 . A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:
 adjusting and setting zero points of upper and lower shadow masks that are mounted in upper and lower mask sets to be rotated and revolved and respectively include a plurality of slits, and distances between the upper and lower shadow masks and the substrate;   forming desired slit patterns using the upper and lower shadow masks by relatively moving the upper and lower mask sets; and   forming the dielectric layer and the conductor layer in the vacuum deposition using the slit patterns.   
     
     
         10 . The method of manufacturing a multi-layer chip capacitor according to  claim 9 , further comprising forming a thermally decomposable releasing layer on the substrate before the setting. 
     
     
         11 . The method of manufacturing a multi-layer chip capacitor according to  claim 9 , further comprising controlling the mask sets to move in the height direction to prevent deposition layers formed on the substrate from being damaged by the shadow masks after the formation of the deposition layers and to be spaced apart from the substrate, and to be positioned in the horizontal direction defined as the width direction and the longitudinal direction. 
     
     
         12 . A method of manufacturing a multi-layer chip capacitor by the vacuum deposition, the method comprising: carrying out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source and by controlling positions of the mask set in the X-, Y-, and Z-axes (the X-axis is the width direction, the Y-axis is the longitudinal direction, and the Z-axis is the height direction) to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once. 
     
     
         13 . A multi-layer chip capacitor manufactured by the method of manufacturing the multi-layer chip capacitor according to  claim 12 . 
     
     
         14 . A method of manufacturing a multi-layer chip capacitor by the vacuum deposition, the method comprising: adjusting slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once. 
     
     
         15 . A multi-layer chip capacitor manufactured by the method of manufacturing the multi-layer chip capacitor according to  claim 14 .