Short channel semiconductor devices with reduced halo diffusion

Abstract

A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

What is claimed is: 
     
         1 . A short channel semiconductor device comprising:
 a gate electrode on a substrate;   source/drain regions on the substrate on each side of the gate electrode;   halo regions under the source/drain regions, wherein the halo regions are separated from the bottom of the gate electrode and from each other.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the gate length is 24 nm to 26 nm, and the separation distance between the halo regions is 8 nm to 10 nm. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein the halo regions are separated from the bottom of the gate electrode by 10 nm. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the halo regions have a peak concentration separated from each other by a distance of 16 nm to 18 nm. 
     
     
         5 . The semiconductor device according to  claim 1 , further comprising source/drain extension regions on the substrate on each side of the gate electrode, wherein the halo regions are formed under the extension regions. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein the source/drain regions comprise epitaxially grown silicon carbon, in-situ doped with phosphorous. 
     
     
         7 . The semiconductor device according to  claim 6 , wherein:
 the halo regions comprise boron implanted in the substrate; and   the extension regions comprise arsenic implanted in the substrate.   
     
     
         8 . The semiconductor device according to  claim 1 , wherein the gate electrode comprises a replacement metal gate electrode. 
     
     
         9 . The semiconductor device according to  claim 8 , further comprising a high-k dielectric layer between the gate electrode and the substrate. 
     
     
         10 . A device comprising:
 first and second gates on a substrate;   first spacers on each side of the first gate and second spacers on each side of the second gate;   first source/drain extension regions on the substrate on each side of the first gate and second source/drain extension regions on the substrate on each side of the second gate;   first source/drain regions on the substrate on each side of the first gate and second source/drain regions on the substrate on each side of the second gate; and   first boron implanted halo regions under the first source/drain extension regions and second arsenic implanted halo regions under the second source/drain extension regions,   wherein the first halo regions are separated from the bottom of the first gate electrode and from each other, and the second halo regions are separated from the bottom of the second gate electrode and from each other.   
     
     
         11 . The device according to  claim 10 , wherein the first source/drain extension regions comprise arsenic implanted in the substrate, and the second source/drain extension regions comprise boron implanted in the substrate. 
     
     
         12 . The device according to  claim 10 , wherein the first source/drain regions comprise in-situ phosphorous doped epitaxially grown silicon carbon, and the second source/drain regions comprise in-situ doped epitaxially grown silicon germanium. 
     
     
         13 . The device according to  claim 10 , further comprising a dielectric layer on the substrate surrounding the first and second spacers. 
     
     
         14 . The device according to  claim 10 , wherein each of the first and second gates comprises a replacement metal gate. 
     
     
         15 . The device according to  claim 14 , further comprising a high-k dielectric layer between the substrate and each of the first and second gate electrodes. 
     
     
         16 . The semiconductor device according to  claim 10 , wherein a gate length of each of the first and second gate electrodes is 24 nm to 26 nm, and a separation distance between the first halo regions and between the second halo regions is 8 nm to 10 nm. 
     
     
         17 . The semiconductor device according to  claim 10 , wherein the first and second halo regions are separated from the bottom of the first and second gate electrodes, respectively, by 10 nm. 
     
     
         18 . The semiconductor device according to  claim 10 , wherein the first and second halo regions each have a peak concentration separated from each other by a distance of 16 nm to 18 nm. 
     
     
         19 . A device comprising:
 first and second metal gates on a substrate;   a high-k dielectric layer between the substrate and each of the first and second gate electrodes   first spacers on each side of the first gate and second spacers on each side of the second gate;   a dielectric layer on the substrate surrounding the first and second spacers   first arsenic implanted source/drain extension regions on the substrate on each side of the first gate and second boron implanted source/drain extension regions on the substrate on each side of the second gate;   first in-situ phosphorous doped epitaxially grown silicon carbon source/drain regions on the substrate on each side of the first gate and second in-situ doped epitaxially grown silicon germanium source/drain regions on the substrate on each side of the second gate; and   first boron implanted halo regions under the first source/drain extension regions and second arsenic implanted halo regions under the second source/drain extension regions,   wherein the first halo regions are separated from the bottom of the first gate electrode and from each other, and the second halo regions are separated from the bottom of the second gate electrode, and   wherein a gate length of each of the first and second gate electrodes is 24 nm to 26 nm, and a separation distance between the first halo regions and between the second halo regions is 8 nm to 10 nm.   
     
     
         20 . The semiconductor device according to  claim 19 , wherein:
 the first and second halo regions are separated from the bottom of the first and second gate electrodes, respectively, by 10 nm; and   the first and second halo regions each have a peak concentration separated from each other by a distance of 16 nm to 18 nm.