Semiconductor memory device for reducing bit line coupling noise

Abstract

A semiconductor memory device including: first and second memory cell arrays each including at least one word line, at least three bit lines, and memory cells; and a sense amplifier area disposed between the first and second memory cell arrays and including a sense amplifier circuit for sensing and amplifying data of the memory cells, wherein the at least three bit lines of the first memory cell array and the at least three bit lines of the second memory cell array extend in a first direction and the at least three bit lines of the first and the second memory cell arrays are respectively connected to data lines disposed in a second direction, and wherein a bit line located between two of the at least three bit lines of each of the first and the second memory cell arrays is connected to an outermost data line of the data lines.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 first and second memory cell arrays each comprising a plurality of word lines, bit lines disposed to intersect the word lines, and a plurality of memory cells disposed at intersections between the word lines and the bit lines; and   a sense amplifier area disposed between the first and the second memory cell arrays and comprising sense amplifier circuits for sensing and amplifying data of the memory cells,   wherein bit lines of the first memory cell array and bit lines of the second memory cell array extend into the sense amplifier area, and wherein a portion of a first bit line in at least one of the first and the second memory cell arrays has a width greater than a portion of the first bit line in the sense amplifier area.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein a distance between the portion of the first bit line and a second bit line in the sense amplifier area is greater than a distance between the portion of the first bit line and a third bit line in the at least one of the first and the second memory cell arrays. 
     
     
         3 . The semiconductor memory device of  claim 2 , wherein the second bit line is adjacent to the portion of the first bit line in the sense amplifier area and the third bit line is adjacent to the portion of the first bit line in the at least one of the first and second memory cell arrays. 
     
     
         4 . The semiconductor memory device of  claim 1 , wherein the portion of the first bit line in the at least one of the first and the second memory cell arrays has a resistive component that is less than a resistive component of the portion of the first bit line in the sense amplifier area. 
     
     
         5 . The semiconductor memory device of  claim 1 , wherein the semiconductor memory device is included in a memory chip of a memory module, and wherein the memory chip is mounted on a printed circuit board. 
     
     
         6 . The semiconductor memory device of  claim 1 , wherein the semiconductor memory device is included in a system having a controller for controlling the semiconductor memory device through a bus.