Method of providing an operating voltage in a memory device and a memory controller for the memory device

Abstract

A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

What is claimed is: 
     
         1 . A method of providing an operating voltage in a memory device, the method comprising:
 applying a first read voltage to a selected word line of a NAND string;   applying a first pass voltage to at least one unselected word line among unselected word lines adjacent to the selected word line of the NAND string;   applying a second pass voltage to at least one other unselected word lines of the NAND string;   applying a second read voltage to the selected word line of the NAND string;   applying a third pass voltage to at least one unselected word line to which the first pass voltage is applied; and   applying a fourth pass voltage to at least one other unselected word lines to which the second pass voltage is applied;   wherein a level of the first pass voltage is higher than a level of the second pass voltage,   wherein the level of the first pass voltage is different from the level of the third pass voltage.   
     
     
         2 . The method of  claim 1 , wherein if a level of the first read voltage is higher than a level of the second read voltage, the level of the first pass voltage is higher than the level of the third pass voltage,
 wherein if the level of the first read voltage is lower than the level of the second read voltage, the level of the first pass voltage is lower than the level of the third pass voltage.   
     
     
         3 . The method of  claim 1 , wherein applying the first pass voltage comprises detecting the level of the first read voltage and selecting the level of the first pass voltage according to the level of the first read voltage,
 wherein applying the third pass voltage comprises detecting the level of the second read voltage and selecting the level of the third pass voltage according to the level of the second read voltage.   
     
     
         4 . The method of  claim 1 , wherein applying the second pass voltage includes:
 applying the second pass voltage to at least one other unselected word line among unselected word lines disposed on the bit line side of the selected word line in the NAND string; and   applying the second pass voltage to at least one of the other unselected word lines among unselected word lines disposed on the common source side of the selected word line in the NAND string,   wherein applying the fourth pass voltage includes:   applying the fourth pass voltage to at least one other unselected word line among unselected word lines disposed on the bit line side of the selected word line in the NAND string; and   applying the fourth pass voltage to at least one of the other unselected word lines among unselected word lines disposed on the common source side of the selected word line in the NAND string.   
     
     
         5 . The method of  claim 1 , wherein the selecting and applying the selected higher level of the first pass voltage comprises setting the voltage difference between the first pass voltage and the first read voltage to a predetermined value,
 wherein the selecting and applying the selected higher level of the third pass voltage comprises setting the voltage difference between the third pass voltage and the second read voltage to a predetermined value.   
     
     
         6 . The method of  claim 1 , wherein one of the first read voltage and the second read voltage is a read voltage used in incremental step pulse programming (ISPP) or a read voltage used in a random access read operation. 
     
     
         7 . The method of  claim 1 , wherein the selecting and applying the first pass voltage comprises applying the first pass voltage at different levels according to whether the first read voltage is a negative voltage or not a negative voltage,
 wherein the selecting and applying the third pass voltage comprises applying the third pass voltage at different levels according to whether the second read voltage is a negative voltage or not a negative voltage.   
     
     
         8 . A non-transient computer readable storage medium containing program codes configured for execution by a processor to carry out the method of  claim 1 . 
     
     
         9 . A memory device comprising:
 a memory cell array including a string of memory transistors connected to a plurality of word lines;   a voltage generator configured to provide an operating voltage for an operation in the memory cell array; and   a chip controller configured to control the voltage generator to apply a first read voltage to a selected word line, apply a first pass voltage to at least one unselected word line among unselected word lines adjacent to the selected word line, apply a second pass voltage to the other unselected word lines, apply a second read voltage to the selected word line, apply a third pass voltage to at least one unselected word line to which the first pass voltage is applied, and apply a fourth pass voltage to the other unselected word lines to which the second pass voltage is applied,   wherein a level of the first pass voltage is higher than a level of the second pass voltage,   wherein the level of the first pass voltage is different from the level of the third pass voltage.   
     
     
         10 . The method of  claim 9 , wherein if a level of the first read voltage is higher than a level of the second read voltage, the level of the first pass voltage is higher than the level of the third pass voltage,
 wherein if the level of the first read voltage is lower than the level of the second read voltage, the level of the first pass voltage is lower than the level of the third pass voltage.   
     
     
         11 . The memory device of  claim 9 ,
 wherein the chip controller controls the voltage generator to set the level of the first pass voltage and the level of the third pass voltage respectively based on the level of the first read voltage and the level of the second read voltage.   
     
     
         12 . The memory device of  claim 9 , wherein applying the second pass voltage includes:
 applying the second pass voltage to at least one other unselected word line among unselected word lines disposed on the bit line side of the selected word line in the NAND string; and   applying the second pass voltage to at least one of the other unselected word lines among unselected word lines disposed on the common source side of the selected word line in the NAND string,   wherein applying the fourth pass voltage includes:   applying the fourth pass voltage to at least one other unselected word line among unselected word lines disposed on the bit line side of the selected word line in the NAND string; and   applying the fourth pass voltage to at least one of the other unselected word lines among unselected word lines disposed on the common source side of the selected word line in the NAND string.   
     
     
         13 . The memory device of  claim 9 , wherein the chip controller controls the voltage generator to set the level difference between the first pass voltage and the first read voltage to a predetermined value,
 wherein the chip controller controls the voltage generator to set the level difference between the third pass voltage and the second read voltage to a predetermined value.   
     
     
         14 . The memory device of  claim 9 , wherein one of the first read voltage and the second read voltage is a read voltage used in incremental step pulse programming (ISPP) or a read voltage used in a random access read operation. 
     
     
         15 . The memory device of  claim 9 , wherein the chip controller applies the first pass voltage at different levels according to whether the first read voltage is a negative voltage or not a negative voltage,
 wherein the chip controller applies the third pass voltage at different levels according to whether the second read voltage is a negative voltage or not a negative voltage.   
     
     
         16 . A memory system comprising:
 a memory device including an array of memory transistors connected to a plurality of word lines; and   a memory controller configured to control the memory device to apply a first read voltage to a selected word line, apply a first pass voltage to at least one unselected word line among unselected word lines adjacent to the selected word line, apply a second pass voltage to the other unselected word lines, apply a second read voltage to the selected word line, apply a third pass voltage to at least one unselected word line to which the first pass voltage is applied, and apply a fourth pass voltage to the other unselected word lines to which the second pass voltage is applied,   wherein a level of the first pass voltage is higher than a level of the second pass voltage,   wherein the level of the first pass voltage is different from the level of the third pass voltage.