Continuous Power Transfer Scheme for Two-Wire Serial Wire

Abstract

The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.

What is claimed is: 
     
         1 . An I/O interface circuit for communicating across a transmission medium, comprising:
 a first latch including
 a first transmission input terminal, for receiving a first transmission signal to be transmitted via the transmission medium; 
 a first interface terminal, capable of connection to the transmission medium; 
 a first receive output terminal connected to the first interface terminal, for outputting a first receive signal received from the transmission medium; 
 a first buffer, having an output terminal connected to the first interface terminal, and a data input terminal; and 
 a first mode switch, having (i) two input terminals connected respectively to the first transmission input terminal and to the first receive output terminal, (ii) an output terminal connected to the first buffer's data input terminal, and (iii) a mode select terminal capable of receiving a mode select signal for configuring the first mode switch to pass to the first buffer either the first transmission signal for transmission via the transmission medium or the first receive signal received from the transmission medium. 
   
     
     
         2 . The I/O interface circuit of  claim 1 , further comprising
 a storage device connected to the first buffer,   wherein when the first mode switch is configured to pass the first receive signal to the first buffer, the signal passed through the first mode select switch and input to the first buffer causes the first buffer to synchronously rectify the signal at the first interface terminal such that energy from the signal at the first interface terminal is stored in the storage device.   
     
     
         3 . The I/O interface circuit of  claim 1 , further comprising
 a voltage supply connected to the first buffer,   wherein when the first mode switch is configured to pass the first receive signal to the first buffer, the signal passed through the first mode select switch and input to the first buffer causes the first buffer to reinforce the signal appearing at the first interface terminal with energy from the voltage supply.   
     
     
         4 . The I/O interface circuit of  claim 1 , wherein the first buffer further comprises:
 a latch control terminal capable of receiving a latch control signal for enabling or disabling the first buffer.   
     
     
         5 . The I/O interface circuit of  claim 1 , wherein the first buffer further comprises:
 a complementary transistor pair connected between the data input terminal and the output terminal of the first buffer.   
     
     
         6 . The I/O interface circuit of  claim 5 , wherein the first buffer is a tri-state buffer. 
     
     
         7 . The I/O interface circuit of  claim 1 , further comprising:
 a second transmission input terminal, for receiving a second transmission signal to be transmitted via the transmission medium;   a second interface terminal, capable of connection to the transmission medium;   a second receive output terminal connected to the second interface terminal, for outputting a second receive signal received from the transmission medium;   a second buffer, having an output terminal connected to the second interface terminal, and a data input terminal; and   a second mode switch, having (i) two input terminals connected respectively to the second transmission input terminal and to the second receive output terminal, (ii) an output terminal connected to the second buffer's data input terminal, and (iii) a mode select terminal capable of receiving a mode select signal for configuring the second mode switch to pass to the second buffer either the second transmission signal for transmission via the transmission medium or the second receive signal received from the transmission medium.   
     
     
         8 . The I/O interface circuit of  claim 7 , wherein the transmission medium is suitable for the transmission of a differential signal, and wherein the first and second receive signals and the first and second transmission signals form a differential receive signal and a differential transmission signal, respectively.