Three dimensional floating gate nand memory

Abstract

Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.

What is claimed is: 
     
         1 . A memory array comprising:
 a first memory cell comprising:
 a channel; 
 a first insulator; 
 a floating gate; 
 a second insulator; and 
 a control gate, 
 wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and 
   a second memory cell comprising:
 a channel; 
 a first insulator; 
 a floating gate; 
 a second insulator; and 
 a control gate, 
 wherein the first insulator is positioned between the channel and the floating gate, 
 the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other. 
   
     
     
         2 . The memory array according to  claim 1 , wherein the first insulator in the first and second memory cells is a shared structure and the channel in the first and second memory cells is a shared structure. 
     
     
         3 . The memory array according to  claim 1 ,
 wherein the channel comprises polysilicon, silicon germanium, or gallium nitride, indium gallium nitride, or aluminum gallium nitride;   wherein the first insulator comprises a tunneling oxide material;   wherein the floating gate comprises polysilicon;   wherein the second insulator comprises a multilayer structure of an oxide, a nitride, and an oxide, or other high K dielectric materials; and   wherein the control gate comprises a metal or polysilicon.   
     
     
         4 . The memory array according to  claim 1  further comprising a vertical isolation structure positioned between the first memory cell and the second memory cell. 
     
     
         5 . The memory array according to  claim 4  further comprising a plurality of memory cells positioned along the first axis with a plurality of vertical isolation structures positioned between the memory cells. 
     
     
         6 . The memory array according to  claim 5 , wherein the plurality of memory cells are connected in series. 
     
     
         7 . The memory array according to  claim 1  further comprising a horizontal isolation structure positioned adjacent the control gates of the first and second memory cells. 
     
     
         8 . The memory array according to  claim 7 , wherein the memory array further comprises third and fourth memory cells,
 wherein the third memory cell is positioned adjacent the first memory cell along the second axis and the fourth memory cell is positioned adjacent the second memory cell along the second axis, and   wherein the horizontal isolation structure isolates the first and third memory cells from each and the second and fourth memory cells from each other.   
     
     
         9 . The memory array according to  claim 8 , wherein the control gates of the third and fourth memory cells are adjacent the horizontal isolation structure. 
     
     
         10 . A memory array comprising:
 at least two vertical stacks of memory cells, each vertical stack comprising:
 at least two memory cells, the at least two memory cells positioned along a first axis, each memory cell comprising:
 a channel; 
 a first insulator; 
 a floating gate; 
 a second insulator; and 
 a control gate 
 wherein the first insulator is positioned between the control gate and the floating gate, the second insulator is positioned between the floating gate and the channel, and the control gate, the first insulator, the floating gate, the second insulator and the channel are positioned along a second axis, 
 
 wherein the first axis and the second axis are perpendicular to each other; 
 and at least one vertical isolation structure positioned between the first and the second memory cell; and 
   at least one horizontal isolation structure, wherein the at least one horizontal isolation structure isolates a first vertical stack of memory cells from a second vertical stack of memory cells.   
     
     
         11 . The memory array according to  claim 10 , wherein the at least two memory cells within the first vertical stack are connected in series and the at least two memory cells within the second vertical stack are connected in series. 
     
     
         12 . The memory array according to  claim 10 , wherein the memory cells of the first vertical stack have a configuration that is opposite the configuration of the memory cells of the second vertical stack. 
     
     
         13 . The memory array according to  claim 10 , wherein the channels of the memory cells of the first vertical stack are a shared structure and the first insulators of the memory cells of the first vertical stack are a shared structure. 
     
     
         14 . The memory array according to  claim 10 , wherein the first and second vertical stacks are formed from a single stack of bilayer films. 
     
     
         15 . The memory array according to  claim 10  further comprising a plurality of vertical stacks, wherein at least the horizontal isolation structure and the two adjacent vertical stacks form a first row. 
     
     
         16 . The memory array according to  claim 15 , wherein the memory array comprises a plurality of rows, with each row being configured so that the vertical stacks of each adjacent row are offset from one another. 
     
     
         17 . A method of making a memory array, the method comprising:
 depositing a bilayer stack of alternating insulating material and floating gate material;   etching a first void in the stack;   depositing a first insulating material on at least the walls of the first void forming a second void;   depositing channel material in the second void;   etching a third void in the stack, the third void being substantially circular and surrounding the channel material;   selectively etching portions of the polysilicon layers adjacent the third void forming fourth voids, wherein the fourth voids are generally orthogonal to each other;   depositing a second insulating material on the surfaces of the fourth voids;   depositing control gate material on the second insulating material, forming a sixth void; and   depositing isolating material in the sixth void.   
     
     
         18 . The method according to  claim 17 , wherein the step of depositing the second insulating material is accomplished using dielectric deposition 
     
     
         19 . The method according to  claim 17 , wherein the step of selective etching portions of the polysilicon layers is accomplished using chemical etching using BCl 3 , H 2 , SF 6 , or O 2 . 
     
     
         20 . The method according to  claim 17  further comprising vertical etching between deposition of the control gate material and deposition of the isolating material.