Method and device for lowering the impedance of a transistor

Abstract

A method and circuit for lowering impedance of a transistor bridge having two pairs of cooperating transistors, comprising receiving a pair of DC input signals which enable activation of one of the pairs of transistors, the activation providing a path for the DC input signals through the two activated transistors, the pair of DC input signals having voltages differing from each other by a first amount; and applying a second pair of DC signals each to a different gate of the two activated transistors, the second pair of DC signals having voltages differing from each other by a second amount that is greater than the first amount, wherein as a result of the second amount being greater than the first amount, impedances of the two activated transistors are lower as compared to if the pair of DC input signals were used in substitution for the second pair of signals.

What is claimed is: 
     
         1 . A method for lowering impedance of a transistor bridge having first and second pairs of cooperating transistors, the method comprising the steps of:
 receiving a pair of DC input signals which enable activation of one of the pairs of transistors, said activation providing a path for the DC input signals through the two activated transistors, said pair of DC input signals having voltages differing from each other by a first amount; and   applying a second pair of DC signals each to a different gate of the two activated transistors, said second pair of DC signals having voltages differing from each other by a second amount that is greater than said first amount,   wherein as a result of said second amount being greater than said first amount, impedances of the two activated transistors are lower as compared to if said pair of DC input signals were instead used in substitution for said second pair of DC signals.   
     
     
         2 . The method as claimed in  claim 1 , wherein the transistor bridge is a Field Effect Transistor (FET) bridge and said transistors are FETs. 
     
     
         3 . The method as claimed in  claim 1 , further comprising the step of generating said second pair of DC signals, the generating step occurring before the applying step. 
     
     
         4 . The method as claimed in  claim 3 , wherein the generating step includes generating, after a first signal of said second pair of DC signals has already been generated, the other signal of said second pair of DC signals by inverting said first signal. 
     
     
         5 . The method as claimed in  claim 1 , wherein said second amount is between two and four times said first amount. 
     
     
         6 . A circuit for lowering impedance of a transistor bridge having first and second cooperating pairs of transistors, the bridge receiving a pair of DC input signals which enable activation of one of the cooperating pairs of transistors, the activation providing a path for the DC input signals through the two activated transistors, the pair of DC input signals having voltages differing from each other by a first amount, and the circuit comprising:
 means for generating a second pair of DC signals having voltages differing from each other by a second amount that is greater than said first amount; and   means for applying said second pair of DC signals each to a different gate of the two activated transistors,   wherein as a result of said second amount being greater than said first amount, impedances of the two activated transistors are lower as compared to if said pair of DC input signals were instead used in substitution for said second pair of DC signals.   
     
     
         7 . The circuit as claimed in  claim 6 , wherein said transistor bridge is a Field Effect Transistor (FET) bridge and said transistors are FETs. 
     
     
         8 . The circuit as claimed in  claim 6 , wherein said generating means comprises a charge conditioning circuit. 
     
     
         9 . The circuit as claimed in  claim 8 , wherein said charge conditioning circuit includes a monostable multivibrator and a number of capacitors configured for voltage boosting and in communication with said monostable multivibrator, said monostable multivibrator for regulating charging of said capacitors. 
     
     
         10 . The circuit as claimed in  claim 9 , wherein said charge conditioning circuit includes an inverter, said inverter including an input and an output, and when one of said second pair of DC signals is received at said inverter input the other of said second pair of DC signals is outputted at said inverter output. 
     
     
         11 . The circuit as claimed in  claim 6 , wherein said applying means includes a number of level sensing transistors and a number of switching transistors. 
     
     
         12 . The circuit as claimed in  claim 11 , wherein said level sensing transistors are P-channel transistors and said switching transistors are N-channel transistors. 
     
     
         13 . The circuit as claimed in  claim 6 , wherein said second amount is between two and four times said first amount. 
     
     
         14 . The circuit as claimed in  claim 6 , wherein said second pair of DC signals are substantially of equal and opposite magnitude.