US2013262752A1PendingUtilityA1

Efficient use of hybrid media in cache architectures

Assignee: VIOLIN MEMORY INCPriority: Dec 31, 2008Filed: Feb 13, 2013Published: Oct 3, 2013
Est. expiryDec 31, 2028(~2.4 yrs left)· nominal 20-yr term from priority
G06F 12/0866G06F 2212/7211G06F 12/08G06F 12/0806G06F 12/0897G06F 2212/225G06F 12/0246G06F 2212/6042G06F 12/02G06F 9/06
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Claims

Abstract

A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus comprising:
 a manager configured to control access to a memory device:
 the memory device having:
 first memory type elements; and 
 second type elements capable of performing a limited number of write operations, 
 
   wherein the manager causes data to be stored in first memory type elements and selects data to be moved from the first memory type elements in accordance with a policy that adjusts a maximum write rate of the selected data being moved from the first memory type elements to the second memory type elements based on a current number of times that a write operation has been performed to memory elements of the second memory type elements and a lifetime of the second memory type elements.   
     
     
         2 . The apparatus of  claim 1 , further comprising the memory device. 
     
     
         3 . The apparatus of  claim 2 , wherein the second memory type element is a flash memory element. 
     
     
         4 . The apparatus of  claim 1 , wherein the second memory type element is configured to have a plurality of blocks having a block size and a predetermined maximum number of writes is permitted for each block. 
     
     
         5 . The apparatus of  claim 4 , wherein a number of times that a write operation has been performed to selected group of blocks of the plurality of blocks is used to determine maximum write rate to be permitted for write operations to the selected group of blocks. 
     
     
         6 . The apparatus of  claim 1 , wherein the lifetime of the second memory type elements is an epoch time during which the second memory type elements meet a predetermined lifetime specification. 
     
     
         7 . The apparatus of  claim 1 , wherein the lifetime of the second memory type elements is an epoch time during which the second memory type elements meet a predetermined lifetime guarantee. 
     
     
         8 . The apparatus of  claim 1 , wherein a quantity of data to be moved from the first memory element type to the second memory element type is selected such that a substantially optimum block size of the second memory element type is written. 
     
     
         9 . The apparatus of  claim 1 , wherein a quantity of data to be moved from the first memory element type to the second memory element type is selected such that an optimum block size of the second memory element type is written. 
     
     
         10 . The apparatus of  claim 1 , wherein the selected data to be moved from the first memory type elements is discarded when no block of the second memory type elements is available for writing a block size of the data to be moved from the first memory type elements. 
     
     
         11 . The apparatus of  claim 1 , wherein data includes associated data and metadata and the metadata and associated data is selectively stored in either the first memory type elements or the second memory type elements. 
     
     
         12 . The apparatus of  claim 4  wherein the first memory type elements have a first block size and the second memory type elements have a second block size and data is moved from the first memory type elements to the second memory type elements when there is no available block of memory in the first memory type elements to store new data. 
     
     
         13 . The apparatus of  claim 1  wherein the first memory type elements are a volatile memory. 
     
     
         14 . The apparatus of  claim 1 , wherein the second memory type elements are a non-volatile memory type 
     
     
         15 . The apparatus of  claim 14 , wherein the non-volatile memory type is a flash memory type. 
     
     
         16 . A method for managing a memory device, comprising:
 configuring a manager controlling access to a memory device comprising:
 first memory type elements; and 
 second memory type elements capable of performing a limited number of write operations; 
 to perform the steps of:
 receiving data for caching; 
 writing the received data into the first memory type elements; 
 select data stored in the first memory type elements for writing to second memory type elements based on factors including a size and an age of the data, 
 wherein a maximum write rate to the second memory type elements is calculated from the predetermined maximum number of writes and a lifetime of the second memory type elements. 
 
   
     
     
         17 . The method of  claim 1 , wherein the selection of data for writing to second memory type elements in includes a factor selected from data type, data source, user application type, or location of servers in communication with the memory device. 
     
     
         17 . The method of  claim 15 , further comprising virtualizing the received data such that the physical address of data stored in the memory device is hidden from a user. 
     
     
         18 . The method of  claim 15 , wherein each of the first memory type elements and the second memory type elements is configured to have a first block size and a second block size, respectively, and when data having a size less than a block size of the memory element to which the data is to be written has been received, storage locations in a physical block are allocated to accommodate the data such that a plurality of writes of data of less than the physical block size are made to the physical block.

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