Automatic optimal integrated circuit generator from algorithms and specification

Abstract

Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

What is claimed is: 
     
         1 . A method to automatically design a custom integrated circuit, comprising:
 receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit;   automatically generating a computer architecture with at least one of: programmable processor, co-processor, programmable specialized accelerator, non-programmable specialized accelerator, data memory, cache, data pre-fetch circuit, program pre-fetch circuit, circuit supporting instruction set functionality/encoding/compression, register, static and dynamic branch prediction circuit, control register, stack operation circuit, circular buffer, data address circuit, pipeline depth and functionality circuit, scan/tap controller;   automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots;   continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis;   automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit;   automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and   automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.   
     
     
         2 . The method of  claim 1 , comprising performing static profiling of the computer readable code. 
     
     
         3 . The method of  claim 1 , comprising performing dynamic profiling of the computer readable code. 
     
     
         4 . The method of  claim 1 , comprising selecting an architecture based on the computer readable code. 
     
     
         5 . The method of  claim 1 , comprising optimizing the architecture based on static and dynamic profiling of the computer readable code. 
     
     
         6 . The method of  claim 1 , comprising compiling the computer readable code into assembly code. 
     
     
         7 . The method of  claim 7 , comprising linking the assembly code to generate firmware for the selected architecture. 
     
     
         8 . The method of  claim 7 , comprising performing cycle accurate simulation of the firmware. 
     
     
         9 . The method of  claim 7 , comprising performing dynamic profiling of the firmware. 
     
     
         10 . The method of  claim 9 , comprising optimizing the architecture based on profiled firmware. 
     
     
         11 . The method of  claim 7 , comprising optimizing the architecture based on the assembly code. 
     
     
         12 . The method of  claim 1 , comprising generating register transfer level code for the selected architecture. 
     
     
         13 . The method of  claim 12 , comprising performing synthesis of the RTL code. 
     
     
         14 . A system to automatically design a custom integrated circuit, comprising:
 a. means for receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit;   b. means for automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints;   c. means for automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots;   d. means for continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis;   e. means for automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit;   f. means for automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and   g. means for automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.   
     
     
         15 . The system of  claim 14 , comprising means for performing static and dynamic profiling of the computer readable code. 
     
     
         16 . The system of  claim 14 , comprising means for selecting an architecture based on the computer readable code. 
     
     
         17 . The system of  claim 14 , comprising means for optimizing the architecture based on profiles of the computer readable code. 
     
     
         18 . The system of  claim 14 , comprising a compiler to convert the computer readable code into assembly code. 
     
     
         19 . The system of  claim 14 , comprising a cycle accurate simulator to test the firmware. 
     
     
         20 . The system of  claim 14 , comprising register transfer level code generator for the selected architecture.