Non-volatile memory device formed with etch stop layer in shallow trench isolation region

Abstract

A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

1 . A method comprising:
 forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer;   etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and   forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.   
     
     
         2 . The method of  claim 1 , wherein forming the STI region comprises:
 etching a STI trench in the substrate by a second etch, the STI trench comprising a bottom and sides;   forming a STI liner on the bottom and sides of the STI trench;   forming the etch stop layer over the STI liner; and   forming an oxide fill over the etch stop layer.   
     
     
         3 . The method of  claim 2 , further comprising etching a portion of the etch stop layer located on the bottom of the STI trench by a third etch before forming the oxide fill. 
     
     
         4 . The method of  claim 3 , wherein the third etch comprises one of an anisotropic nitride etch and a CH x F y +O 2  etch. 
     
     
         5 . The method of  claim 2 , wherein the first etch comprises etching the oxide fill. 
     
     
         6 . The method of  claim 1 , wherein the etch stop layer comprises nitride. 
     
     
         7 . The method of  claim 1 , wherein the floating gate comprises a floating gate material comprising one of polysilicon, titanium nitride (TiN), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN), and wherein forming the floating gate comprises conformal deposition of the floating gate material and etching of the deposited floating gate material by a fourth etch. 
     
     
         8 . The method of  claim 7 , wherein the floating gate comprises sloped sides having an angle of about 10 degrees, and wherein the fourth etch comprises CH x F y +O 2 . 
     
     
         9 . The method of  claim 1 , wherein the recess in the STI region comprises a bottom and sides comprising the etch stop layer. 
     
     
         10 . The method of  claim 1 , wherein the recess in the STI region comprises a bottom and sides, wherein the bottom of the recess comprises an oxide fill of the STI region, and wherein the sides of the recess comprise the etch stop layer. 
     
     
         11 . A device, comprising:
 a substrate;   a shallow trench isolation (STI) region located in the substrate, the STI region comprising an etch stop layer, and further comprising a recess in the STI region, the recess having a bottom and sides, wherein the sides of the recess are defined by the etch stop layer; and   a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by the etch stop layer.   
     
     
         12 . The device of  claim 11 , wherein the etch stop layer comprises nitride, and, wherein the floating gate comprises one of polysilicon, titanium nitride (TiN), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN). 
     
     
         13 . The device of  claim 11 , wherein the etch stop layer is located over a STI liner of the STI region. 
     
     
         14 . The device of  claim 11 , wherein the bottom of the recess comprises the etch stop layer. 
     
     
         15 . The device of  claim 11 , wherein the bottom of the recess comprises an oxide fill of the STI region. 
     
     
         16 . The device of  claim 11 , wherein the floating gate comprises sloped sides, and wherein the sloped sides of the floating gate have an angle of about 10 degrees. 
     
     
         17 . The device of  claim 11 , further comprising tunnel oxide located directly underneath the floating gate on the substrate, and well regions located in the substrate underneath the tunnel oxide. 
     
     
         18 . The device of  claim 11 , further comprising:
 a gate dielectric layer located over the floating gate; and   a control gate located over the gate dielectric layer, wherein a portion of the control gate extends into the recess in the STI region.   
     
     
         19 . The device of  claim 18 , wherein the gate dielectric layer is located directly on a portion of the etch stop layer that is located at the bottom of the recess in the STI region. 
     
     
         20 . The device of  claim 18 , wherein the gate dielectric layer is located directly on an oxide fill located at the bottom of the recess in the STI region.