Memory element, stacking, memory matrix and method for operation

Abstract

Disclosed is a memory element, a stack, and to a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V 0 , this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V 1 , it can be transferred into the likewise high-impedance state 1. By applying a read voltage V R , the magnitude of which is smaller than the write voltages V 0 and V 1 , the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.

1 .- 36 . (canceled) 
     
     
         37 . The method according to  claim 47 , wherein at least one of the two voltage levels is at least as great, with regard to magnitude, as the write voltages V 0  and V 1  of the memory elements P and Q. 
     
     
         38 . The method according to  claim 47 , wherein upon application of a read voltage V R , the magnitude of which is smaller than the write voltages V 0  and V 1 , the two states 0 and 1 of the memory elements P and Q become manifest in different electrical resistance values of the memory elements P and Q. 
     
     
         39 . The method according to  claim 47 , wherein the memory elements P and Q have at least a first stable state 0 and a second stable state 1 which, by applying a first write voltage can be transferred into the state 0 and, by applying a second write voltage, can be transferred into the state 1, wherein, upon application of a read voltage, the amount of which is smaller than the write voltages, the two states 0 and 1 are manifested in different electrical resistance values of the memory element, wherein the memory elements comprise a series circuit of at least two memory cells A and B having at least two memory cells A and B which have, respectively, a stable state A 0  and B) having higher electrical resistance, and a stable state A 1  and B 1  having lower electrical resistance. 
     
     
         40 . The method according to  claim 38 , wherein at least one of the memory elements P or Q is acted upon by the read voltage V R  thereof. 
     
     
         41 . The method according to  claim 47 , wherein after application of the voltage levels of variables K and L to the poles of the memory elements P and Q, a parallel circuit of the memory elements P and Q is acted upon by a voltage that acts on both memory elements P and Q as read voltage V R . 
     
     
         42 . The method according to  claim 47 , wherein the temporal characteristics of the currents which are driven through the array upon application of voltage levels of variables K and L to the poles of the memory elements P and Q are evaluated to determine the truth value of the logic operation. 
     
     
         43 . The method according to  claim 47 , wherein memory elements P and Q having nominally identical write voltages V 0 , V 1  and read voltages V R  are selected. 
     
     
         44 . The method according to  claim 47  wherein a stack comprising memory elements P and Q are directed to a stack and/or a memory matrix directed to a memory matrix is selected as the array comprising memory elements. 
     
     
         45 . The method according to  claim 47 , wherein the memory elements P and Q have different polarities are each switched between the voltage level of the variable K and that of the variable L. 
     
     
         46 . The method according to  claim 47 , wherein both memory elements P and Q are initialized in the defined state before they are acted upon by the voltage levels of the variables K and L. 
     
     
         47 . A method for determining the truth value of a logic operation of two variables K and L
 in an array comprising at least two memory elements P and Q each having at least one stable state 0 and one stable state 1, which can each be transferred into the state 0 by applying a first write voltage V 0 , and into the state 1 by applying a second write voltage V 1 ,   wherein the variables K and L are provided in the form of two voltage levels assigned to the truth values 0 and 1,   wherein the magnitude of the difference between the two voltage levels is at least as great as the write voltages V 0  and V 1  of the memory elements P and Q,   at least one of the two poles P 1 , P 2  of the memory element P is acted upon by the voltage level of the variable K, and at least one of the two poles Q 1 , Q 2  of the memory element Q is acted upon by the voltage level of the variable L, wherein   
       memory elements P and Q are selected, which each contain a series of at least two memory cells A and B, which have, respectively, a stable state A 0  and B 0  having higher electrical resistance, and a stable state A 1  and B 1  having lower electrical resistance, wherein, in each of the two memory elements P and Q, the state 0 is coded in the combination of states A 0  and B 1 , and the state 1 is coded in the combination of states A 1  and B 0 .