US2013308672A1PendingUtilityA1

Chip array structure for laser diodes and packaging device for the same

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Assignee: PAN JIN-SHANPriority: May 18, 2012Filed: Jul 11, 2012Published: Nov 21, 2013
Est. expiryMay 18, 2032(~5.8 yrs left)· nominal 20-yr term from priority
H10H 29/142H01S 5/02345H01S 5/423H01S 5/42
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Claims

Abstract

A chip array structure for laser diodes, formed on an active surface of a semiconductor chip produced from a semiconductor process includes a plurality of light-emitting elements in an array arrangement, at least one insulation wall, at least two wire bond areas and a plurality of connection electrodes. The insulation wall separates the light-emitting elements into at least two light-emitting districts. The wire bond areas are positioned respective to the corresponding light-emitting districts. The connection electrodes electrically couple the wire bond areas with the corresponding light-emitting districts. The wire bond areas have independent electrodes, and the light-emitting districts are electrically isolated by the insulation wall.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A chip array structure for laser diodes, formed on an active surface of a semiconductor chip produced by a semiconductor process, comprising:
 a plurality of light-emitting elements in an array arrangement;   at least one insulation wall for separating the plurality of light-emitting elements into at least two light-emitting districts;   at least two wire bond areas, located at positions respective to the at least two light-emitting districts; and   a plurality of connection electrodes individually for electrically connecting the at least two wire bond areas to the respective at least two light-emitting districts;   wherein each of the at least two light-emitting districts is electrically independent, the semiconductor chip has a bottom surface including thereon an electrode layer having a polarity different to that of the at least two wire bond areas, and the at least two wire bond areas have individual but identical polarity.   
     
     
         2 . The chip array structure for laser diodes according  claim 1 , wherein said plurality of light-emitting elements are selected from a group of vertical cavity surface emitting Lasers (VCSEL), horizontal cavity surface emitting Lasers (HCSEL), and resonant cavity light emitting diodes (RCLED). 
     
     
         3 . The chip array structure for laser diodes according  claim 1 , wherein said at least two light-emitting districts have individual geometrical configurations. 
     
     
         4 . The chip array structure for laser diodes according  claim 1 , wherein each of said at least two light-emitting districts includes an individual amount of said light-emitting elements and an individual current input so as to control brightness of said light-emitting district. 
     
     
         5 . A packaging device for a chip array structure for laser diodes, comprising:
 a metal substrate, having a support surface to carry thereon a first electrode area, at least one second electrode area and at least one third electrode area;   an insulation structure for electrically separating the first electrode area, each of the at least one second electrode area and each of the at least one third electrode area;   a semiconductor chip, produced by a semiconductor process, having thereof an active surface to include thereon a plurality of light-emitting elements in an array arrangement, at least one insulation wall for separating the plurality of light-emitting elements into at least two light-emitting districts, at least two wire bond areas located at positions respective to the at least two light-emitting districts, and a plurality of connection electrodes individually for electrically connecting the at least two wire bond areas to the respective at least two light-emitting districts;   a conductive glue, located, thus for establishing electric connection, between a bottom surface of the semiconductor chip and the first electrode area a plurality of metal wires, and   a plurality of connection electrodes individually for electrically connecting the at least two wire bond areas to the respective at least two light-emitting districts;   wherein each of the at least two light-emitting districts is electrically independent, a polarity of the bottom surface is different to that of the at least two wire bond areas, and the at least two wire bond areas have individual but identical polarity.   
     
     
         6 . The packaging device for a chip array structure for laser diodes according to  claim 5 , wherein said metal substrate is made of a material selected from a group of copper, aluminum, gold, and related alloys, and said plurality of light-emitting elements are selected from a group of vertical cavity surface emitting Lasers (VCSEL), horizontal cavity surface emitting Lasers (HCSEL), and resonant cavity light emitting diodes (RCLED). 
     
     
         7 . The packaging device for a chip array structure for laser diodes according to  claim 5 , wherein said at least two light-emitting districts have individual geometrical configurations. 
     
     
         8 . The packaging device for a chip array structure for laser diodes according to  claim 5 , wherein each of said at least two light-emitting districts includes an individual amount of said light-emitting elements and an individual current input so as to control brightness of said light-emitting district. 
     
     
         9 . The packaging device for a chip array structure for laser diodes according to  claim 5 , further including a circuit board engaged thereon said metal substrate, the circuit board being made of a material selected from a group of a low temperature co-fired ceramic (LTCC), a high temperature co-fired ceramic (HTCC) and a plastics. 
     
     
         10 . The packaging device for a chip array structure for laser diodes according to  claim 9 , further including a plurality of leads extended from said circuit board and electrically coupled with said at least one second electrode area, or either said at least one third electrode area or said first electrode area.

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