Maintaining processor context before entering power saving mode

Abstract

A CPU automatically preserves the CPU context in a computer memory that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

What is claimed is: 
     
         1 . A data processing apparatus, comprising:
 a processor operable in a first power domain;   an on-chip cache memory operable for storing data processed by the processor, the on-chip cache memory operable in a second power domain, the data processing apparatus operable to:
 maintain context of the processor at the on-chip cache memory before entering a power saving mode, the context available to restore the processor to a state existing at a time of initiation of the power saving mode; and 
 power down the first power domain during the power saving mode. 
   
     
     
         2 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises state of an application program to be executed by the processor. 
     
     
         3 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises memory contents of the processor. 
     
     
         4 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises internal state of the processor. 
     
     
         5 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises state of an operating system. 
     
     
         6 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises contents of general purpose registers of the processor. 
     
     
         7 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises contents of special purpose registers of the processor. 
     
     
         8 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises contents of peripheral registers of the processor. 
     
     
         9 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises content of a data cache of the processor. 
     
     
         10 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises content of an instruction cache of the processor. 
     
     
         11 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises content of a program memory of the processor. 
     
     
         12 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises content of a data memory of the processor. 
     
     
         13 . The data processing apparatus of  claim 1 , wherein the context of the processor comprises contents of Northbridge registers. 
     
     
         14 . The data processing apparatus of  claim 1 , wherein, during a resume operation, the data processing apparatus is further operable to power up the first power domain and transfer the context of the processor from the on-chip cache to the processor. 
     
     
         15 . The data processing apparatus of  claim 1 , wherein, during a resume operation, the data processing apparatus is further operable to restore the processor to the state existing at the time of initiation of the power saving mode. 
     
     
         16 . A method, comprising:
 operating a processor in a first power domain, the processor coupled to an on-chip cache memory that is operable for storing data processed by the processor, the on-chip cache memory operating in a second power domain;   maintaining context of the processor at the on-chip cache memory before entering a power saving mode, the context available to restore the processor to a state existing at a time of initiation of the power saving mode, and   powering down the first power domain during the power saving mode.   
     
     
         17 . The method of  claim 16 , wherein the context of the processor comprises state of an application program to be executed by the processor. 
     
     
         18 . The method of  claim 16 , wherein the context of the processor comprises memory contents of the processor. 
     
     
         19 . The method of  claim 16 , wherein the context of the processor comprises internal state of the processor. 
     
     
         20 . The method of  claim 16 , wherein the context of the processor comprises state of an operating system. 
     
     
         21 . The method of  claim 16 , wherein the context of the processor comprises contents of general purpose registers of the processor. 
     
     
         22 . The method of  claim 16 , wherein the context of the processor comprises contents of special purpose registers of the processor. 
     
     
         23 . The method of  claim 16 , wherein the context of the processor comprises contents of peripheral registers of the processor. 
     
     
         24 . The method of  claim 16 , wherein the context of the processor comprises content of a data cache of the processor. 
     
     
         25 . The method of  claim 16 , wherein the context of the processor comprises content of an instruction cache of the processor. 
     
     
         26 . The method of  claim 16 , wherein the context of the processor comprises content of a program memory of the processor. 
     
     
         27 . The method of  claim 16 , wherein the context of the processor comprises content of a data memory of the processor. 
     
     
         28 . The method of  claim 16 , wherein the context of the processor comprises contents of Northbridge registers. 
     
     
         29 . The method of  claim 16 , further comprising, during a resume operation, powering up the first power domain and transferring the context of the processor from the on-chip cache to the processor. 
     
     
         30 . The method of  claim 16 , further comprising, during a resume operation, restoring the processor to the state existing at the time of initiation of the power saving mode. 
     
     
         31 . A data processing system, comprising:
 a processor and a first memory, internal to the processor, configured to be powered in a first power domain;   a second memory coupled to the processor, the second memory configured to be powered in a second power domain; and   a third memory coupled to the processor, the third memory configured to be powered in a third power domain such that the first power domain, the second power domain, and the third power domain can be independently powered up and independently powered down.   
     
     
         32 . The data processing system of  claim 31 , wherein the second memory is used to store context data of the processor when the first power domain is powered down and the second power domain is powered up. 
     
     
         33 . The data processing system of  claim 32 , wherein the context data of the processor comprises state of an application program to be executed by the processor. 
     
     
         34 . The data processing system of  claim 32 , wherein the context data of the processor comprises memory contents of the processor. 
     
     
         35 . The data processing system of  claim 32 , wherein the context data of the processor comprises internal state of the processor. 
     
     
         36 . The data processing system of  claim 32 , wherein the context data of the processor comprises state of an operating system. 
     
     
         37 . The data processing system of  claim 32 , wherein the context data of the processor comprises contents of general purpose registers of the processor. 
     
     
         38 . The data processing system of  claim 32 , wherein the context data of the processor comprises contents of special purpose registers of the processor. 
     
     
         39 . The data processing system of  claim 32 , wherein the context data of the processor comprises contents of peripheral registers of the processor. 
     
     
         40 . The data processing system of  claim 32 , wherein the context data of the processor comprises content of a data cache of the processor. 
     
     
         41 . The data processing system of  claim 32 , wherein the context data of the processor comprises content of an instruction cache of the processor. 
     
     
         42 . The data processing system of  claim 32 , wherein the context data of the processor comprises content of a program memory of the processor. 
     
     
         43 . The data processing system of  claim 32 , wherein the context data of the processor comprises content of a data memory of the processor. 
     
     
         44 . The data processing system of  claim 32 , wherein the context data of the processor comprises contents of Northbridge registers. 
     
     
         45 . The data processing system of  claim 32 , wherein, during a resume operation, the data processing system is further operable to power up the first power domain and transfer the context data of the processor from the on-chip cache to the processor. 
     
     
         46 . The data processing system of  claim 32 , wherein, during a resume operation, the data processing system is further operable to restore the processor to the state existing when the first power domain was powered down. 
     
     
         47 . A data processing system, comprising:
 a processor configured to be powered in a first power domain;   a first cache memory configured to be powered in a second power domain; and   a second cache memory configured to be powered in a third power domain, such that the first power domain, the second power domain, and the third power domain can be independently powered up and independently powered down.   
     
     
         48 . The data processing system of  claim 47 , further comprising a third memory configured to be powered in a fourth power domain, such that the first power domain, the second power domain, the third power domain, and the fourth power domain can be independently powered up and individually powered down. 
     
     
         49 . The data processing system of  claim 47 , wherein at least one of the first cache memory and the second cache memory is used to store context data of the processor when the first power domain is powered down. 
     
     
         50 . The data processing system of  claim 49 , wherein the context data of the processor comprises state of an application program to be executed by the processor. 
     
     
         51 . The data processing system of  claim 49 , wherein the context data of the processor comprises memory contents of the processor. 
     
     
         52 . The data processing system of  claim 49 , wherein the context data of the processor comprises internal state of the processor. 
     
     
         53 . The data processing system of  claim 49 , wherein the context data of the processor comprises state of an operating system. 
     
     
         54 . The data processing system of  claim 49 , wherein the context data of the processor comprises contents of general purpose registers of the processor. 
     
     
         55 . The data processing system of  claim 49 , wherein the context data of the processor comprises contents of special purpose registers of the processor. 
     
     
         56 . The data processing system of  claim 49 , wherein the context data of the processor comprises contents of peripheral registers of the processor. 
     
     
         57 . The data processing system of  claim 49 , wherein the context data of the processor comprises content of a data cache of the processor. 
     
     
         58 . The data processing system of  claim 49 , wherein the context data of the processor comprises content of an instruction cache of the processor. 
     
     
         59 . The data processing system of  claim 49 , wherein the context data of the processor comprises content of a program memory of the processor. 
     
     
         60 . The data processing system of  claim 49 , wherein the context data of the processor comprises content of a data memory of the processor. 
     
     
         61 . The data processing system of  claim 49 , wherein the context data of the processor comprises contents of Northbridge registers. 
     
     
         62 . The data processing system of  claim 49 , wherein, during a resume operation, the data processing system is further operable to power up the first power domain and transfer the context data of the processor from the on-chip cache to the processor. 
     
     
         63 . The data processing system of  claim 49 , wherein, during a resume operation, the data processing system is further operable to restore the processor to the state existing at a time the first power domain was powered down. 
     
     
         64 . A data processing system, comprising:
 a processor;   a first memory accessible to the processor;   a second memory accessible to the processor, wherein power to the second memory is controlled separately from power to the processor and to the first memory, wherein power is maintained to the second memory when power is removed from the processor, the second memory for maintaining a portion of the context of the processor when power is removed from the processor; and   a third memory external to the processor and accessible to the processor, wherein power to the third memory is controlled separately from power to the processor and to the first and second memories, the third memory for preserving other portions of the context of the processor when power is removed from the processor.   
     
     
         65 . The data processing system of  claim 64 , wherein the first memory is a cache memory. 
     
     
         66 . The data processing system of  claim 64 , wherein the second memory is a cache memory. 
     
     
         67 . The data processing system of  claim 64 , wherein the second memory is accessible only to the processor. 
     
     
         68 . The data processing system of  claim 64 , wherein the second memory is internal to the processor. 
     
     
         69 . The data processing system of  claim 64 , wherein the second memory is external to the processor. 
     
     
         70 . The data processing system of  claim 64 , wherein power is maintained to the third memory when power is removed from the processor during a power saving mode.