Semiconductor device having non-orthogonal element

Abstract

The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

1 . A semiconductor device, comprising:
 a first gate structure segment and a collinear second gate structure segment;   a third gate structure segment and a collinear fourth gate structure segment; and   an interconnection structure extending from the first gate structure segment to the fourth gate structure segment, wherein the interconnection structure is disposed above the first gate structure segment and the fourth gate structure segment, and wherein the interconnect structure has a planar bottom surface, the planar bottom surface extending from on the first gate structure to on the fourth gate structure.   
     
     
         2 . The device of  claim 1 , wherein the interconnection structure includes:
 a first portion disposed on the first gate structure segment;   a second portion disposed on the fourth gate structure segment, wherein the first and second portions are substantially parallel; and   a third portion connecting the first and second portions, wherein the third portion is substantially perpendicular to the first and second portions, wherein each of the first, second and third portions are co-planar.   
     
     
         3 . The device of  claim 1 , further comprising:
 a contact plug co-planar with the interconnection structure.   
     
     
         4 . The device of  claim 1 , further comprising:
 spacer elements formed on sidewalls of the first and fourth gate structure segments, wherein the interconnection structure is disposed on a top surface of the spacer elements.   
     
     
         5 . The device of  claim 1 , wherein the interconnection structure includes tungsten. 
     
     
         6 . The device of  claim 1 , wherein the first gate structure segment is non-orthogonal with respect to a third gate structure segment such that an imaginary line drawn from a first end of the first gate structure segment to a first end of the third gate structure segment is non-orthogonal with respect to a sidewall of the first gate structure segment. 
     
     
         7 . A semiconductor device, comprising:
 a substrate;   a first gate structure disposed on the substrate;   a second gate structure disposed on the substrate adjacent and parallel to the first gate structure, wherein the first gate structure is non-orthogonally disposed with respect to the second gate structure;   a third gate structure aligned with and spaced a first distance from the first gate structure, wherein the third gate structure is parallel to the second gate structure; and   an interconnection structure extending between the second gate structure and the third gate structure, wherein the interconnection structure includes a conductive material disposed in a single layer extending from the second gate structure to the third gate structure; and   a contact element connected to one of the first, second and third gate structures, wherein the conductive material is co-planar with the contact element.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the first gate structure is non-orthogonal with respect to the second gate structure such that an imaginary line drawn from a first end of the first gate structure to a first end of the second gate structure is non-orthogonal with respect to a sidewall of at least one of the first and second gate structures. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the first end of the first gate structure and the first end of the second gate structure are disposed on an isolation region. 
     
     
         10 . The semiconductor device of  claim 7 , wherein a first end of the first gate structure is non-orthogonal with respect to a sidewall of the first gate structure. 
     
     
         11 . The semiconductor device of  claim 7 , further comprising:
 a fourth gate structure aligned with the second gate structure and spaced a second distance from the second gate structure.   
     
     
         12 . The semiconductor device of  claim 7 , wherein the interconnection is not co-planar with a plane extending through the second gate structure and the third gate structure. 
     
     
         13 . (canceled) 
     
     
         14 . The semiconductor device of  claim 11 , wherein the first distance and the second distance are substantially equal, and wherein the space between the third gate structure and the first gate structure is offset from the space between the fourth gate structure and the second gate structure in a direction parallel to the length of the first gate structure. 
     
     
         15 .- 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a gate layer formed on a substrate, the gate layer including:
 a first gate structure and a collinear second gate structure; 
 a third gate structure and a collinear fourth gate structure; and 
   a contact layer disposed above the gate layer, the contact layer including:
 an interconnection structure extending from the first gate structure to the fourth gate structure; and 
 a contact plug connected one of the first, second, third and fourth gate structure. 
   
     
     
         22 . The semiconductor device of  claim 21 , wherein the contact plug is disposed in a dielectric layer of the contact layer. 
     
     
         23 . The semiconductor device of  claim 21 , wherein the interconnection structure extending from the first gate structure to the fourth gate structure includes tungsten. 
     
     
         24 . The semiconductor device of  claim 21 , wherein the interconnection structure directly interfaces with the first gate structure and the second gate structure. 
     
     
         25 . The device of  claim 1 , wherein the bottom surface of the interconnect structure includes tungsten.