Gate driving apparatus

Abstract

A gate driving apparatus is disclosed. The gate driving apparatus includes a first gate driving chip and N second gate driving chips, wherein N is positive integer. The first gate driving chip has a first input pin and a first current output pin. The first gate driving chip receives a reference electrical signal by the first input pin, and generates a reference current according to the reference electrical signal. The first current output pin is used for outputting the reference current. Each of the second gate driving chips has a current input pin for receiving the reference current and a second current output pin for outputting the reference current. The first gate driving chip and the second gate driving chips generate at least a first output signal and at least N second output signals according to the reference current.

What is claimed is: 
     
         1 . A gate driving apparatus, comprising:
 a first gate driving chip, the first gate driving chip comprises a input pin and a first current output pin, the first gate driving chip receives a reference electrical signal through the input pin and generates a reference current according to the reference electrical signal, the first current output pin outputs the reference current; and   N second gate driving chips, the second gate driving chips are coupled with each other in series, each of the second gate driving chips comprises a current input pin and a second current output pin, the reference current is received through the current input pin and outputted by the second current output pin, the current input pin of the first chip of the second gate driving chips is coupled to the first current output pin of the first gate driving chip to receive the reference current, N is a positive integer,   wherein, the first gate driving chip and the second gate driving chips further respectively generate at least one first output signal and at least N second output signals according to the reference current.   
     
     
         2 . The gate driving apparatus as claimed in  claim 1 , wherein the first gate driving chip comprises:
 a voltage-current converter, coupled to the input pin to receive the reference electrical signal, wherein the reference electrical signal is a reference voltage, the voltage-current converter generates the reference current by converting the reference voltage.   
     
     
         3 . The gate driving apparatus as claimed in  claim 2 , wherein the voltage-current converter comprises:
 at least one current mirror, to receive the reference voltage as a bias voltage and generates the reference current according to the reference voltage, the current mirror is coupled to the first current output pin, and the current mirror mirrors the reference current to output the reference current from the first current output pin.   
     
     
         4 . The gate driving apparatus as claimed in  claim 1 , wherein the first gate driving chip comprises:
 at least one current mirror, configured to receive the reference electrical signal of current signal, and mirrors the reference electrical signal to generate the reference current, the current mirror is coupled to the first current output pin, and the reference current is outputted by the first current output pin.   
     
     
         5 . The gate driving apparatus as claimed in  claim 1 , wherein each of the second gate driving chips comprises:
 at least one current mirror, configured to receive the reference electrical signal of current signal, and mirrors the reference electrical signal to generate the reference current, the current mirror is coupled to the first current output pin, and the reference current is outputted by the first current output pin.   
     
     
         6 . The gate driving apparatus as claimed in  claim 1 , wherein the first gate driving chip comprises:
 a reference electrical signal generator, coupled to the input pin and configured to generate the reference electrical signal.   
     
     
         7 . The gate driving apparatus as claimed in  claim 6 , wherein the first gate driving chip further comprises:
 a selector, coupled between a coupling path of the reference electrical signal generator and the input pin, though the selector, the first gate driving chip selectively receives the reference electrical signal generated from outside of the first gate driving chip or the reference electrical signal generated by the reference signal generator according to a selection signal.   
     
     
         8 . The gate driving apparatus as claimed in  claim 6 , wherein the reference electrical signal generator is a current source, configured to generate the reference electrical signal of current signal as the reference electrical current, wherein the current source is coupled to the first current output pin through a first transmission line, and the reference current is transmitted to the first current output pin through the first transmission line. 
     
     
         9 . The gate driving apparatus as claimed in  claim 8 , wherein each of the second gate driving chips comprises a second transmission line, the second transmission line is coupled between the current input pin of each of the second gate driving chips and the second current output pin of each of the second gate driving chips. 
     
     
         10 . The gate driving apparatus as claimed in  claim 1 , wherein further comprising:
 a programmable reference electrical signal generator, coupled to the input pin, the programmable reference electrical signal generator comprises a programmable interface to receive a command signal, the programmable reference electrical signal generator generates the reference electrical signal according to the command signal.   
     
     
         11 . The gate driving apparatus as claimed in  claim 10 , wherein the programmable reference electrical signal generator comprises:
 a command register, configured to receive and store temporary the command signal; and   a reference electrical signal generator, coupled to the command register and the input pin, the reference electrical signal is generated and/or adjusted according to the command signal.   
     
     
         12 . The gate driving apparatus as claimed in  claim 10 , wherein the programmable interface is a serial peripheral interface. 
     
     
         13 . The gate driving apparatus as claimed in  claim 1 , wherein the first gate driving chip comprises:
 a first functional block circuit, configured to receive the reference current and generates the first output signal according to the reference current,   each of the second gate driving chips comprises:   a second functional block circuit, configured to receive the reference current and generates the at least one second output signal according to the reference current.   
     
     
         14 . A gate driving apparatus, comprising:
 a plurality of gate driving chips, each of the gate driving chips comprises a common pin, the common pins of the gate driving chips are coupled to each other; and   a current generator, one end of the current generator is coupled to the common pin of each of the gate driving chips, another end of the current generator is coupled to a first reference voltage, a reference current is provided between the common pin of each of the gate driving chips and the first reference voltage by the current generator,   wherein, each of the gate driving chips generates at least one output signal, each of the gate driving chips is enabled to transition the output signal between the first reference voltage and a second reference voltage according to a control signal.   
     
     
         15 . The gate driving apparatus as claimed in  claim 14 , wherein each of the gate driving chips comprises at least one gate driving circuit, the gate driving circuit comprises:
 a first transistor, comprising a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor is coupled to the second reference voltage, the second terminal of the first transistor generates the output signal, wherein the control terminal of the first transistor receives the control signal; and   a second transistor, comprising a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor is coupled to the second terminal of the first transistor, the control terminal of the second transistor receives the control signal, and the second terminal of the second transistor is coupled to the corresponding common pin.   
     
     
         16 . The gate driving apparatus as claimed in  claim 15 , wherein when the first reference voltage is a reference ground voltage, the second reference voltage is a driving voltage, when the first reference voltage is a driving voltage, the second reference voltage is the reference ground voltage. 
     
     
         17 . The gate driving apparatus as claimed in  claim 15 , wherein the gate driving circuit further comprises:
 a plurality of sub-driving circuits, configured to receive the output signal, each of the sub-driving circuits comprising:
 a sub-controller, configured to generate a sub-control signal; 
 a third transistor, having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor receives the output signal, the second terminal of the third transistor generates a sub-output signal, wherein the control terminal of the third transistor receives the sub-control signal; and 
   a fourth transistor, comprising a first terminal, the second terminal, and a control terminal, the first terminal of the fourth transistor is coupled to the sub-output signal, the second terminal of the fourth transistor is coupled to a third reference voltage, wherein the control terminal of the fourth transistor receives the sub-control signal.   
     
     
         18 . The gate driving apparatus as claimed in  claim 14 , wherein the current generator is a resistor, the resistor is connected in series between the common pin of each of the gate driving chips and the first reference voltage. 
     
     
         19 . The gate driving apparatus as claimed in  claim 14 , wherein the resistor is a variable resistor. 
     
     
         20 . The gate driving apparatus as claimed in  claim 14 , wherein the current generator is a current source, configured to generate the reference current.