Identification of mistimed forcing of values in design simulation
Abstract
A computer identifies a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced. In response to identifying the storage element, an indication of the storage element and the associated clock signal are stored in a database. In response to receiving an input indicating the value of the storage element is to be forced during simulation, a determination is made by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal. In response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, an indication that forcing of the value is mistimed is output.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of data processing, comprising:
a computer identifying a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced, wherein the storage element has an associated clock signal; in response to identifying the storage element, recording in a database an indication of the storage element and the associated clock signal; in response to receiving an input indicating the value of the storage element is to be forced during simulation of the integrated circuit design using the simulation model, determining by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal; and in response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, outputting an indication that forcing of the value is mistimed.
2 . The method of claim 1 , wherein the identifying includes identifying the storage element from a simulation file specifying one or more values to be asserted during simulation.
3 . The method of claim 1 , wherein the storage element is one of a set including a latch and a register.
4 . The method of claim 1 , wherein the recording includes recording a name of the storage element and a name of the clock signal.
5 . The method of claim 1 , wherein the outputting comprises outputting an indication of a timing relative to the clock signal at which the value is to be forced.
6 . The method of claim 1 , and further comprising simulating the integrated circuit design utilizing one of a set including event simulation and cycle simulation.
7 . The method of claim 1 , wherein:
the value of the storage element is forced to a particular value; and the method further comprises automatically modifying timing of application of the particular value to the storage element so that forcing of the value is not mistimed.
8 . A program product, comprising:
a computer-readable storage medium; and program code stored on the computer-readable storage medium and executable by a computer system to cause the computer system to:
identify a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced, wherein the storage element has an associated clock signal;
in response to identifying the storage element, record in a database an indication of the storage element and the associated clock signal;
in response to receiving an input indicating the value of the storage element is to be forced during simulation of the integrated circuit design using the simulation model, determine by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal; and
in response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, output an indication that forcing of the value is mistimed.
9 . The program product of claim 8 , wherein the program code causes the computer system to identify the storage element from a simulation file specifying one or more values to be asserted during simulation.
10 . The program product of claim 8 , wherein the storage element is one of a set including a latch and a register.
11 . The program product of claim 8 , wherein the program code causes the computer system to record a name of the storage element and a name of the clock signal.
12 . The program product of claim 8 , wherein the program code causes the computer system to output an indication of a timing relative to the clock signal at which the value is to be forced.
13 . The program product of claim 8 , wherein the program code further causes the computer system to simulate the integrated circuit design utilizing one of a set including event simulation and cycle simulation.
14 . The program product of claim 8 , wherein:
the value of the storage element is forced to a particular value; and the program code further causes the computer system to automatically modify timing of application of the particular value to the storage element so that forcing of the value is not mistimed.
15 . A data processing system, comprising:
a processor; data storage coupled to the processor; and program code stored on the computer-readable storage medium and executable by the processor to cause the data processing system to:
identify a storage element in a simulation model of an integrated circuit design that, during simulation of the integrated circuit design using the simulation model, is subject to having its value forced, wherein the storage element has an associated clock signal;
in response to identifying the storage element, record in a database an indication of the storage element and the associated clock signal;
in response to receiving an input indicating the value of the storage element is to be forced during simulation of the integrated circuit design using the simulation model, determine by reference to the database whether or not forcing of the value is mistimed with reference to the associated clock signal; and
in response to a determination that the forcing of the value as indicated by the input is mistimed with reference to the associated clock signal, output an indication that forcing of the value is mistimed.
16 . The data processing system of claim 15 , wherein the program code causes the data processing system to identify the storage element from a simulation file specifying one or more values to be asserted during simulation.
17 . The data processing system of claim 15 , wherein the storage element is one of a set including a latch and a register.
18 . The data processing system of claim 15 , wherein the program code causes the data processing system to record a name of the storage element and a name of the clock signal.
19 . The data processing system of claim 15 , wherein the program code causes the data processing system to output an indication of a timing relative to the clock signal at which the value is to be forced.
20 . The data processing system of claim 15 , wherein the program code further causes the data processing system to simulate the integrated circuit design utilizing one of a set including event simulation and cycle simulation.
21 . The data processing system of claim 15 , wherein:
the value of the storage element is forced to a particular value; and the program code further causes the data processing system to automatically modify timing of application of the particular value to the storage element so that forcing of the value is not mistimed.Join the waitlist — get patent alerts
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