Method and Apparatus for Hierarchical Wafer Quality Predictive Modeling

Abstract

An apparatus for performing enhanced wafer quality prediction in a semiconductor manufacturing process includes memory, for storing historical data relating to the semiconductor manufacturing process, and at least one processor in operative communication with the memory. The processor is operative: to obtain data including tensor format wafer processing conditions, historical wafer quality measurements and/or prior knowledge relating to at least one of the semiconductor manufacturing process and wafer quality; to build a hierarchical prediction model including at least the tensor format wafer processing conditions; and to predict wafer quality for a newly fabricated wafer based at least on the hierarchical prediction model and corresponding tensor format wafer processing conditions.

What is claimed is: 
     
         1 . An apparatus for performing enhanced wafer quality prediction in a semiconductor manufacturing process, the apparatus comprising:
 memory for storing at least historical data relating to the semiconductor manufacturing process; and   at least one processor in operative communication with the memory, the at least one processor being operative: to obtain data including at least one of tensor format wafer processing conditions, historical wafer quality measurements and prior knowledge relating to at least one of the semiconductor manufacturing process and wafer quality; to build a hierarchical prediction model including at least the tensor format wafer processing conditions; and to predict wafer quality for a newly fabricated wafer based at least on the hierarchical prediction model and corresponding tensor format wafer processing conditions.   
     
     
         2 . The apparatus of  claim 1 , wherein the at least one processor, to build the hierarchical prediction model, is further operative: to decompose higher-order weight tensors into lower-order tensors; to approximate the lower-order tensors based at least in part on the prior knowledge; and to minimize a prediction error and optimizing an approximation of the lower-order tensors as a function of the prediction error. 
     
     
         3 . The apparatus of  claim 2 , wherein the at least one processor is operative to decompose the higher-order weight tensors into lower-order tensors using a canonical polyadic decomposition. 
     
     
         4 . The apparatus of  claim 2 , wherein the at least one processor is operative to optimize the approximation of the lower-order tensors using a block coordinate decent methodology. 
     
     
         5 . The apparatus of  claim 2 , wherein the at least one processor is further operative to update at least one of the tensor format wafer processing conditions, historical wafer quality measurements and prior knowledge as a function of an approximation of the lower-order tensors. 
     
     
         6 . The apparatus of  claim 1 , wherein the at least one processor is operative build the hierarchical prediction model using tensor inputs without converting the tensor inputs to corresponding vectors. 
     
     
         7 . The apparatus of  claim 1 , wherein the at least one processor is operative to utilize an output associated with at least one of a wafer quality prediction and the hierarchical prediction model to perform advanced process control (APC) relating to the semiconductor manufacturing process. 
     
     
         8 . The apparatus of  claim 1 , wherein the at least one processor is operative to utilize an output associated with at least one of a wafer quality prediction and the hierarchical prediction model to perform wafer quality fault detection and classification (FDC). 
     
     
         9 . A hierarchical modeling module for enhancing wafer quality prediction in a semiconductor manufacturing process, the hierarchical modeling module comprising:
 a tensor decomposition module operative to receive data including at least one of tensor format wafer processing conditions and historical wafer quality measurements, and to decompose higher-order weight tensors into lower-order tensors;   a tensor approximation module operative to receive prior knowledge relating to at least one of the semiconductor manufacturing process and wafer quality, and to approximate the lower-order tensors based at least in part on the prior knowledge; and   an optimization module operative to minimize a prediction error and optimizing an approximation of the lower-order tensors as a function of the prediction error;   wherein an output generated by at least one the tensor decomposition module, the tensor approximation module and the optimization module is utilized to build a prediction model for predicting wafer quality for a newly fabricated wafer.   
     
     
         10 . An article of manufacture comprising a computer program product, said computer program product in turn comprising a tangible computer readable storage medium storing in a non-transitory manner executable program instructions which, when executed, implement steps of:
 obtaining data including at least one of tensor format wafer processing conditions, historical wafer quality measurements and prior knowledge relating to at least one of the semiconductor manufacturing process and wafer quality;   building a hierarchical prediction model including at least the tensor format wafer processing conditions; and   predicting wafer quality for a newly fabricated wafer based at least on the hierarchical prediction model and corresponding tensor format wafer processing conditions.