Digital frequency demodulator with low power consumption and related system and method

Abstract

An apparatus includes a frequency counter configured to receive an input signal containing pulses and to output a count value identifying a number of pulses in the input signal during a specified time period. The specified time period encompasses multiple cycles of the input signal. The apparatus also includes a comparator configured to receive the count value, compare the count value to a second value, and provide an output signal based on the comparison. The apparatus further includes a data latch configured to latch the output signal, where the latched value of the output signal represents a demodulated data value. The comparator could be configured to compare the count value to a fixed value associated with a desired frequency of the input signal. The comparator could also be configured to compare the count value in one specified time period to a stored count value from another specified time period.

What is claimed is: 
     
         1 . An apparatus comprising:
 a frequency counter configured to receive an input signal containing pulses and to output a count value identifying a number of pulses in the input signal during a specified time period, the specified time period encompassing multiple cycles of the input signal;   a comparator configured to receive the count value from the frequency counter, compare the count value to a second value, and provide an output signal based on the comparison; and   a data latch configured to latch the output signal, wherein the latched value of the output signal represents a demodulated data value.   
     
     
         2 . The apparatus of  claim 1 , wherein the comparator is configured to compare the count value to a fixed value, the fixed value associated with a desired frequency of the input signal. 
     
     
         3 . The apparatus of  claim 1 , wherein the frequency counter is configured to output multiple count values during multiple specified time periods. 
     
     
         4 . The apparatus of  claim 3 , wherein:
 the apparatus further comprises a prior counter output latch configured to store the count value generated during one of the specified time periods; and   the comparator is configured to compare the count value in another of the specified time periods to the stored count value.   
     
     
         5 . The apparatus of  claim 3 , wherein the frequency counter and the data latch are configured to receive a counter gate signal defining the specified time periods. 
     
     
         6 . The apparatus of  claim 1 , wherein:
 the frequency counter is configured to output the count value in parallel format; and   the comparator is configured to receive the count value in parallel format and the second value in parallel format.   
     
     
         7 . The apparatus of  claim 1 , wherein the data latch comprises a D flip-flop. 
     
     
         8 . A system comprising:
 a receive path configured to process an incoming wireless signal and generate demodulated data, the receive path comprising a digital frequency demodulator;   wherein the digital frequency demodulator comprises:
 a frequency counter configured to receive an input signal containing pulses and to output a count value identifying a number of pulses in the input signal during a specified time period, the specified time period encompassing multiple cycles of the input signal; 
 a comparator configured to receive the count value from the frequency counter, compare the count value to a second value, and provide an output signal based on the comparison; and 
 a data latch configured to latch the output signal, wherein the latched value of the output signal represents a demodulated data value. 
   
     
     
         9 . The system of  claim 8 , wherein the receive path is configured to generate an intermediate frequency signal using the incoming wireless signal, the input signal to the frequency counter comprising the intermediate frequency signal. 
     
     
         10 . The system of  claim 8 , wherein the comparator is configured to compare the count value to a fixed value, the fixed value associated with a desired frequency of the input signal. 
     
     
         11 . The system of  claim 8 , wherein the frequency counter is configured to output multiple count values during multiple specified time periods. 
     
     
         12 . The system of  claim 11 , wherein:
 the digital frequency demodulator further comprises a prior counter output latch configured to store the count value generated during one of the specified time periods; and   the comparator is configured to compare the count value in another of the specified time periods to the stored count value.   
     
     
         13 . The system of  claim 11 , wherein the frequency counter and the data latch are configured to receive a counter gate signal defining the specified time periods. 
     
     
         14 . The system of  claim 8 , wherein:
 the frequency counter is configured to output the count value in parallel format; and   the comparator is configured to receive the count value in parallel format and the second value in parallel format.   
     
     
         15 . The system of  claim 8 , wherein the receive path further comprises:
 a first amplifier configured to amplify the incoming wireless signal;   a filter configured to filter the amplified wireless signal;   a mixer configured to down-convert the filtered wireless signal; and   a second amplifier configured to amplify the down-converted signal, the second amplifier having an output coupled to an input of the frequency counter.   
     
     
         16 . The system of  claim 8 , further comprising:
 a transceiver including the receive path;   a sensor configured to sense at least one characteristic of a patient;   an actuator configured to modify the at least one characteristic of the patient; and   a control unit configured to control the actuator.   
     
     
         17 . A method comprising:
 receiving an input signal containing pulses;   generating a count value identifying a number of pulses in the input signal during a specified time period, the specified time period encompassing multiple cycles of the input signal;   comparing the count value to a second value;   providing an output signal based on the comparison; and   latching the output signal, wherein the latched value of the output signal represents a demodulated data value.   
     
     
         18 . The method of  claim 17 , wherein comparing the count value comprises comparing the count value to a fixed value, the fixed value associated with a desired frequency of the input signal. 
     
     
         19 . The method of  claim 17 , wherein:
 generating the count value, comparing the count value, providing the output signal, and latching the output signal are repeated during multiple specified time periods;   the method further comprises storing the count value generated during one of the specified time periods; and   comparing the count value comprises comparing the count value in another of the specified time periods to the stored count value.   
     
     
         20 . The method of  claim 17 , further comprising:
 generating an intermediate frequency signal using an incoming wireless signal, the input signal comprising the intermediate frequency signal.