High fill-factor efficient vertical-cavity surface emitting laser arrays

Abstract

An array of vertical-cavity surface emitting lasers (VCSELs) may be fabricated with very high fill-factors, thereby enabling very high output power densities during pulse, quasi-continuous wave (QCW), and continuous wave (CW) operation. This high fill-factor is achieved using asymmetrical pillars in a rectangular packing scheme as opposed prior art pillar shapes and packing schemes. The use of asymmetrical pillars maintains high efficiency operation of VCSELs by maintaining minimal current injection distance from the metal contacts to the laser active region and by maintaining efficient waste heat extraction from the VCSEL. This packing scheme for very high fill-factor VCSEL arrays is directly applicable for next generation high-power, substrate removed, VCSEL arrays.

1 . A method comprising:
 forming semiconductor processing features on a semiconductor region to form a two-dimensional (2D) array of vertical-cavity surface emitting laser (VCSEL) apertures, each aperture having a length along a long axis of the aperture and a width along a short axis of the aperture, wherein
 a ratio of the aperture length to the aperture width is at least two-to-one, 
 at least 10% of a surface area of the semiconductor region comprises surface areas of the VCSEL apertures, and 
 a first portion of the semiconductor processing features comprises one or more etched trenches disposed between the VCSEL apertures. 
   
     
     
         2 . The method of  claim 1 , wherein:
 the aperture length is less than a length of the semiconductor region and the aperture width is less than a width of the semiconductor region;   a ratio of the aperture width to a width of the semiconductor processing features is at most two-to-one; and   the ratio of the aperture length to the aperture width is at least four-to-one.   
     
     
         3 . The method of  claim 1 , wherein:
 a top un-etched surface area of the semiconductor region is greater than 47% of the surface area of the semiconductor region; and   at least 25% of the surface area of the semiconductor region comprises surface areas of the VCSEL apertures.   
     
     
         4 . The method of  claim 1 , wherein:
 each row of the 2D array includes a plurality of the VCSEL apertures; and   each of the VCSEL apertures are separated along their short and long axes by the semiconductor processing features.   
     
     
         5 . The method of  claim 4 , wherein the semiconductor processing features separating consecutive rows of the 2D array are aligned and/or offset. 
     
     
         6 . The method of  claim 1 , wherein each of the VCSEL apertures comprises a relatively rectangular shape or a relatively oval shape. 
     
     
         7 . The method of  claim 1 , wherein:
 each of the VCSEL apertures comprises a polygon of non-parallel sides; and   the non-parallel sides are angled to suppress in-plane optical feedback.   
     
     
         8 . The method of  claim 1 , wherein a second portion of the semiconductor processing features comprises oxidized portions of an aperture layer of the 2D array of VCSELs and/or a pattern of non-conductive material implanted into the semiconductor region. 
     
     
         9 . The method of  claim 8 , wherein:
 the first portion of the semiconductor processing features has a minimum trench width greater than 3 μm; and   the second portion of the semiconductor processing features comprises oxidized portions of an aperture layer of the 2D array of VCSELs having a minimum oxide length greater than 3 μm.   
     
     
         10 . An apparatus comprising the 2D array of VCSEL apertures formed according to the method of  claim 1 . 
     
     
         11 . An apparatus comprising:
 a semiconductor region;   a first row of at least one vertical-cavity surface emitting laser (VCSEL) formed on the semiconductor region; and   a second row of at least one VCSEL formed on the semiconductor region and separated from the first row by a current confinement separator; wherein
 each VCSEL includes an aperture having a length and a width, 
 a ratio of the aperture length to the aperture width is at least two-to-one, 
 at least 10% of a surface area of the semiconductor region corresponds to surface areas of the apertures of the first and second rows of VCSELs, and 
 a first portion of the current confinement separator comprises an etched row trench. 
   
     
     
         12 . The apparatus of  claim 11 , wherein:
 each VCSEL further includes an aperture layer forming the aperture and having a width greater than the width of the aperture by a first value; and   a ratio of the aperture width to the sum of the first value and a width of the row trench is at most two-to-one.   
     
     
         13 . The apparatus of  claim 11 , wherein:
 the aperture length is less than a length of the semiconductor region and the aperture width is less than a width of the semiconductor region;   a ratio of the aperture width to a distance between apertures of the VCSELs of the first and second rows is at most two-to-one; and   the ratio of the aperture length to the aperture width is at least four-to-one.   
     
     
         14 . The apparatus of  claim 11 , wherein:
 a top un-etched surface area of the semiconductor region is greater than 47% of the surface area of the semiconductor region; and   at least 25% of the surface area of the semiconductor region corresponds to surface areas of the apertures of the first and second rows of VCSELs.   
     
     
         15 . The apparatus of  claim 11 , wherein the first and second rows of VCSELs each comprise a plurality of VCSELs separated by column trenches. 
     
     
         16 . The apparatus of  claim 15 , wherein a first column trench of the first row of VCSELs is aligned with a second column trench of the second row of VCSELs or is offset with respect to the second column trench of the second row of VCSELs. 
     
     
         17 . The apparatus of  claim 15 , wherein a length of the column trenches is not equal to a width of the row trench. 
     
     
         18 . The apparatus of  claim 11 , wherein each aperture of the VCSELs of the first and second rows comprises a relatively rectangular shape or a relatively oval shape. 
     
     
         19 . The apparatus of  claim 11 , wherein each aperture of the VCSELs of the first and second rows comprises a polygon of non-parallel sides, the sides angled to suppress in-plane optical feedback. 
     
     
         20 . The apparatus of  claim 19 , wherein:
 the first portion of the current confinement separator has a minimum trench width greater than 3 μm;   a second portion of the current confinement separator comprises oxidized portions of an aperture layer of the 2D array of VCSELs and/or a pattern of implanted non-conductive material; and   the second portion of the current confinement separator has a minimum width greater than 3 μm.