US2014030843A1PendingUtilityA1

Ohmic contact of thin film solar cell

66
Assignee: AHMED SHAFAATPriority: Jul 26, 2012Filed: Jul 26, 2012Published: Jan 30, 2014
Est. expiryJul 26, 2032(~6 yrs left)· nominal 20-yr term from priority
H10F 77/1694H10F 77/211H10F 77/128H10F 77/126H10F 77/12H10F 10/167H10F 77/219Y02E10/541B82Y 30/00
66
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A chalcogen-resistant material including at least one of a carbon nanotube layer and a high work function material layer is deposited on a transition metal layer on a substrate. A semiconductor chalcogenide/kesterite material layer is deposited over the chalcogen-resistant material. The carbon nanotubes, if present, can reduce contact resistance by providing direct electrically conductive paths from the transition metal layer through the chalcogen-resistant material and to the semiconductor chalcogenide material. The high work function material layer, if present, can reduce contact resistance by reducing chalcogenization of the transition metal in the transition metal layer. Reduction of the contact resistance can enhance efficiency of a solar cell including the chalcogenide semiconductor material.

Claims

exact text as granted — not AI-modified
1 . A method of forming electrical contact to a transition metal layer, said method comprising:
 depositing a plurality of carbon nanotubes on a surface of a transition metal layer comprising at least one transition metal element;   depositing a semiconductor chalcogenide material layer comprising a semiconductor chalcogenide material directly on said plurality of carbon nanotubes; and   forming a transition metal chalcogenide layer comprising a chalcogenide of said at least one transition metal element by thermal annealing, wherein said thermal annealing is performed at a temperature that induces an interaction between said semiconductor chalcogenide material and said at least one transition metal element of said transition metal layer.   
     
     
         2 . (canceled) 
     
     
         3 . The method of  claim 1 , wherein first portions of said plurality of carbon nanotubes become embedded within said transition metal chalcogenide layer, and second portions of said plurality of carbon nanotubes become embedded in said semiconductor chalcogenide material layer. 
     
     
         4 . The method of  claim 1 , further comprising forming a high work function transition metal element layer comprising at least one elemental metal having a work function greater than 4.6 eV and greater than any work function of said at least one transition metal element directly on a surface of said transition metal layer and said plurality of carbon nanotubes before said semiconductor chalcogenide material layer is deposited. 
     
     
         5 . The method of  claim 4 , wherein first portions of said plurality of carbon nanotubes become embedded within said high work function transition metal element layer after said high work function transition metal element layer is deposited, and second portions of said plurality of carbon nanotubes become embedded in said semiconductor chalcogenide material layer after said semiconductor chalcogenide material layer is deposited. 
     
     
         6 . The method of  claim 4 , wherein said high work function transition metal element layer comprises at least one element selected from Group VIIIB elements, Group IB elements, and Re. 
     
     
         7 . The method of  claim 4 , wherein said high work function transition metal element layer comprises at least one element selected from Co, Ru, Rh, Pd, Os, Ir, Pt, and Au. 
     
     
         8 . The method of  claim 1 , wherein said semiconductor chalcogenide material is a semiconductor sulfide material. 
     
     
         9 . The method of  claim 1 , wherein said at least one transition metal element comprises molybdenum. 
     
     
         10 . The method of  claim 1 , wherein said plurality of carbon nanotubes is predominantly metallic, and is deposited with a random distribution of spatial orientations. 
     
     
         11 . The method of  claim 1 , wherein said transition metal layer consists essentially of said at least one transition metal element. 
     
     
         12 . The method of  claim 11 , wherein said at least one transition metal element is selected from Nb, V, Zn, Ti, Mo, Cr, and W. 
     
     
         13 . The method of  claim 1 , wherein said semiconductor chalcogenide material layer includes a p-n junction therein. 
     
     
         14 . The method of  claim 1 , wherein said semiconductor material layer comprises at least one of CuIn(Se,S) 2  (CIS), CuInGaSe 2  (CIGS), Cu 2 (Zn,Fe)Sn(S,Se) 4 , Ga(S,Se), GaTe, GaAs, In 2 (S,Se) 3 , and InTe, InP, CdTe, Cd(S, Se), ZnTe, Zn 3 P 2 , Pb(Se,S), Zn(S, Se), W(S,Se) 2 , Bi 2 S 3 , Ag 2 S, NiS, ZnO, Cu 2 O, CuO, Cu 2 S, FeS 2 . 
     
     
         15 . The method of  claim 1 , further comprising:
 providing a substrate selected from an insulator substrate including a dielectric material and a metallic substrate including a diffusion barrier layer on the top surface thereof; and   forming said transition metal layer on said substrate.   
     
     
         16 . A method of forming electrical contact to a transition metal layer, said method comprising:
 providing a transition metal layer comprising at least one transition metal element having a work function that does not exceed 4.6 eV thereupon;   forming a high work function transition metal element layer comprising at least one elemental metal having a work function greater than 4.6 eV directly on a surface of said transition metal layer; and   depositing a semiconductor chalcogenide material layer comprising a semiconductor chalcogenide material directly on said high work function transition metal element layer.   
     
     
         17 . The method of  claim 16 , wherein said high work function transition metal element layer consists essentially of said at least one elemental metal, has a contiguous bottom surface contacting said transition metal layer, and has a contiguous top surface contacting said semiconductor chalcogenide material layer. 
     
     
         18 . The method of  claim 16 , further comprising depositing a plurality of carbon nanotubes on said surface of said transition metal layer before forming said high work function transition metal element layer. 
     
     
         19 . The method of  claim 18 , wherein said plurality of carbon nanotubes is predominantly metallic, and is deposited with a random distribution of spatial orientations. 
     
     
         20 . The method of  claim 18 , wherein end portions of said plurality of carbon nanotubes protrude above said high work function transition metal element layer after formation of said high work function transition metal element layer, and said semiconductor chalcogenide material layer is formed directly on said end portions of said plurality of carbon nanotubes. 
     
     
         21 . The method of  claim 18 , wherein said high work function transition metal element layer comprises at least one of platinum and ruthenium. 
     
     
         22 . The method of  claim 16 , wherein said high work function transition metal element layer comprises at least one element selected from Group VIIIB elements, Group IB elements, and Re. 
     
     
         23 . The method of  claim 16 , wherein said high work function transition metal element layer comprises at least one element selected from Co, Ru, Rh, Pd, Os, Ir, Pt, and Au. 
     
     
         24 . The method of  claim 16 , further comprising forming a p-n junction within said semiconductor chalcogenide material layer. 
     
     
         25 . The method of  claim 16 , further comprising providing a substrate selected from an insulator substrate including a dielectric material and a metallic substrate including a diffusion barrier layer on the top surface thereof, wherein said transition metal layer is formed by depositing said at least one transition metal element on said substrate. 
     
     
         26 . The method of  claim 1 , wherein said thermal annealing is a stand-alone anneal process.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.