Semiconductor memory device and manufacturing method thereof

Abstract

The present disclosure relates to a semiconductor memory, device and a method of forming a semiconductor memory device. The semiconductor memory device includes a semiconductor substrate in which isolation regions and active regions are defined, gate lines formed on the semiconductor substrate in a direction crossing the isolation regions, a capping layer configured to define air gaps positioned higher than an upper surface of the semiconductor substrate in the isolation regions.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a semiconductor substrate in which isolation regions and active regions are defined;   gate lines formed on the semiconductor substrate in a direction crossing the isolation regions; and   a capping layer configured to define air gaps positioned higher than an upper surface of the semiconductor substrate in the isolation regions.   
     
     
         2 . The semiconductor memory device of  claim 1 , where the air gaps are formed in trenches defined in the isolation regions of the semiconductor substrate. 
     
     
         3 . The semiconductor memory device of  claim 1 , where the capping layer is higher than the upper surface of the semiconductor substrate in the active regions by about 50 Å to about 150 Å. 
     
     
         4 . The semiconductor memory device of  claim 2 , where the air gap has a same width as a width of the isolation region. 
     
     
         5 . The semiconductor memory device of  claim 2 , further comprising:
 a liner insulation layer formed over a surface of the trenches, where a width of the air gap is a same width as a width of the trenches having the liner isolation layer.   
     
     
         6 . The semiconductor memory device of  claim 1 , further comprising:
 a lower insulation layer to define a lower portion of the air gap in the isolation regions.   
     
     
         7 . The semiconductor memory device of  claim 6 , where the lower insulation layer is formed of a flowable material. 
     
     
         8 . The semiconductor memory device of  claim 7 , where the flowable material is a polisilazane (PSZ). 
     
     
         9 . The semiconductor memory device of  claim 6 , where an upper surface of the lower insulation layer is lower than an upper surface of the semiconductor substrate of the active regions by about 100 Å to about 400 Å. 
     
     
         10 . The semiconductor memory device of  claim 1 , where the capping layer is formed of a non-porous material. 
     
     
         11 . The semiconductor memory device of  claim 10 , where the non-porous material includes a silicon dioxide (SiO 2 ), a silicon nitride (SiN), a silicon oxynitride SiON, or a silicon carbide nitride (SiCN). 
     
     
         12 . The semiconductor memory device of  claim 1 , where the capping layer is formed by atomic layer deposition (ALD). 
     
     
         13 . The semiconductor memory device of  claim 1 , where the capping layer has a thickness of about 5 Å to about 50 Å. 
     
     
         14 . The semiconductor memory device of  claim 1 , where each of the gate lines comprises a plurality of layers stacked on the semiconductor substrate, the plurality of layers including:
 a tunnel insulation layer,   a first conductive layer for a floating gate,   the capping layer, a dielectric layer, and   a second conductive layer for a control gate.   
     
     
         15 . The semiconductor memory device of  claim 14 , further comprising:
 an insulation layer formed between the capping layer and the dielectric layer in the isolation region.   
     
     
         16 . The semiconductor memory device of  claim 15 , were the insulation layer and the capping layer support the upper portion of the air gap. 
     
     
         17 . The semiconductor memory device of  claim 15 , where the insulation layer is formed of a flowable material. 
     
     
         18 . The semiconductor memory device of  claim 17 , where the flowable material is a polisilazane (PSZ) layer. 
     
     
         19 . A semiconductor memory device, comprising:
 a semiconductor substrate in which an isolation region and an active region are defined;   a tunnel insulation layer, a floating gate, a capping layer, a dielectric layer, and a control gate formed over the semiconductor substrate of the active region;   a trench formed in the semiconductor substrate of the isolation region; and   an air gap formed inside the trench,   where the capping layer defines an upper surface of the air gap and where the capping layer is positioned higher than a surface of the semiconductor substrate.   
     
     
         20 . The semiconductor memory device of  claim 19 , where the capping layer is formed of a non-porous material. 
     
     
         21 . The semiconductor memory device of  claim 20 , where the non-porous material includes a silicon dioxide (SiO 2 ), a silicon nitride (SiN) a silicon oxynitride SiON, or a silicon carbide nitride (SiCN). 
     
     
         22 . The semiconductor memory device of  claim 19 , where the capping layer has a thickness of about 5 Å to about 50 Å. 
     
     
         23 . The semiconductor memory device of  claim 19 , further comprising:
 a lower insulation layer filling a lower portion of the trench, where the lower insulation layer is to define a lower surface of the air gap.   
     
     
         24 . A method of manufacturing a semiconductor memory device, the method comprising:
 forming a tunnel insulation layer and a floating gate on a semiconductor substrate of an active region;   forming a trench in the semiconductor substrate of an isolation region;   forming, in the trench, a sacrificial layer having an upper surface positioned higher than a surface of the semiconductor substrate;   forming a capping layer over the sacrificial layer; and   forming an air gap by removing the sacrificial layer without removing the capping layer.   
     
     
         25 . The method of  claim 24 , where the sacrificial layer is a flowable material containing carbon. 
     
     
         26 . The method of  claim 25 , where sacrificial layer is a Spin-On-Carbon (SOC) layer or a photoresist (PR) layer. 
     
     
         27 . The method of  claim 25 , further comprising:
 forming the sacrificial layer by spin coating.   
     
     
         28 . The method of  claim 24 , where forming the sacrificial layer comprises:
 filling the trench with the sacrificial layer;   solidifying the sacrificial layer by performing a heat treatment process; and   etching the sacrificial layer so that an upper surface of the sacrificial layer is positioned higher than the surface of the semiconductor substrate.   
     
     
         29 . The method of  claim 28 , where etching the sacrificial layer further comprises:
 etching the sacrificial layer so that the upper surface of the sacrificial layer is about 50 Å to about 150 Å higher than the surface of the semiconductor substrate.   
     
     
         30 . The method of  claim 24 , further comprising:
 forming a lower insulation layer in a lower portion of the trench before forming the sacrificial layer in the trench.   
     
     
         31 . The method of  claim 30 , where the lower insulation layer is formed of a flowable material. 
     
     
         32 . The met hod of  claim 31 , where the flowable material is a polisilazane (PSZ). 
     
     
         33 . The method of  claim 30 , where forming the lower insulation layer further comprises:
 solidifying the lower insulation layer by performing a heat treatment process; and   etching the lower insulation layer so that an upper surface of the lower insulation layer is lower than the surface of the semiconductor substrate.   
     
     
         34 . The method of  claim 33 , where etching the lower insulation layer further comprises:
 etching the lower insulation layer to be about 100 Å to about 400 Å lower than the surface of the semiconductor substrate.   
     
     
         35 . The method of  claim 24 , where the capping layer is formed of a non-porous material. 
     
     
         36 . The method of  claim 35 , where the non-porous material includes a silicon dioxide (SiO 2 ), a silicon nitride (SiN), a silicon oxynitride SiON, or a silicon carbide nitride (SiCN). 
     
     
         37 . The method of  claim 24 , where the capping layer is formed by atomic layer deposition (ALD) method at a low temperature. 
     
     
         38 . The method of  claim 37 , where the low temperature includes a temperature range of about 50° C. to about 100° C. 
     
     
         39 . The method of  claim 24 , where the capping layer has a thickness of about 5 Å to about 50 Å. 
     
     
         40 . The method of  claim 24 , where removing the sacrificial layer further comprises:
 removing the sacrificial layer via plasma.   
     
     
         41 . The method of  claim 40 , where the plasma is an oxygen, a nitrogen, or a hydrogen plasma. 
     
     
         42 . The method of  claim 24 , further comprising;
 forming an insulation layer on the capping layer after forming the air gap; and   etching the insulation layer so that only a portion of the insulation layer remains in the isolation region over the capping layer.   
     
     
         43 . The method of  claim 42 , where the insulation layer is formed of a flowable material. 
     
     
         44 . The method of  claim 43 , where the flowable material is a polisilazane (PSZ) layer. 
     
     
         45 . A semiconductor memory device comprising;
 a plurality of gate lines formed on a semiconductor substrate; and   a plurality of capping layers formed between the gate lines, wherein the capping layers define a plurality of air gaps between the gate lines.   
     
     
         46 . The semiconductor memory device of  claim 45 , where the capping layers are formed of non porous materials. 
     
     
         47 . The semiconductor memory device of  claim 46 , where the non-porous a materials include silicon dioxide (SiO 2 ), a silicon nitride (SiN), a silicon oxynitride SiON, or a silicon carbide nitride (SiCN). 
     
     
         48 . The semiconductor memory device of  claim 45 , where the plurality of capping layers are formed to have a thickness of about 5 Å to about 50 Å. 
     
     
         49 . The semiconductor memory device of  claim 45 , where a width of an air gap, of the plurality of air gaps, formed at an upper portion of a gate line, of the plurality of gate lines, is narrower than a width of the air gap formed at a lower portion of the gate line. 
     
     
         50 . A method of manufacturing a semiconductor memory is device, the method comprising:
 forming a plurality of gate lines on a semiconductor substrate;   alternately forming sacrificial layers and capping layers on the semiconductor substrate between the gate lines and   forming a plurality of air, defined by the capping layers, between the gate lines by removing the sacrificial layers.   
     
     
         51 . The method of  claim 50 , where alternately forming the sacrificial layers and the capping layers further comprises:
 forming a sacrificial layer between the gate lines;   solidifying the sacrificial layer;   etching the sacrificial layer so that a remaining portion of the sacrificial layer has a predetermined thickness; and   forming the capping layer over the remaining portion of the sacrificial layer.   
     
     
         52 . The method of  claim 50 , where the sacrificial layer is formed of a flowable material containing carbon. 
     
     
         53 . The method of  claim 52 , where the sacrificial layer is a Spin-On-Carbon (SOC) layer or a photoresist (PR) layer. 
     
     
         54 . The method of  claim 52 , where the sacrificial layer is formed by spin coating. 
     
     
         55 . The method of  claim 50 , where the capping layer is formed of a non-porous material. 
     
     
         56 . The method of  claim 50 , where the non-porous layer material includes a silicon dioxide (SiO 2 ), a silicon nitride (SiN), a silicon oxynitride SiON, or a silicon carbide nitride (SiCN). 
     
     
         57 . The method of  claim 50 , where the capping layer is formed by atomic layer deposition (ALD) at a low temperature. 
     
     
         58 . The method of  claim 57 , where the low temperature includes a temperature range of about 50° C. to about 100° C. 
     
     
         59 . The method of  claim 50 , where the capping layer is has a is thickness of about 5 Å to about 50 Å.