Sub-10 nm graphene nanoribbon lattices

Abstract

A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions. The amorphous alumina portions are removed and the remaining dense alumina portions which have an ordered lattice arrangement are employed as an etch mask. After removing the amorphous alumina portions, each dense alumina portion has a width which is also less than 10 nm.

What is claimed is: 
     
         1 . A semiconductor structure comprising an ordered array of graphene nanoribbons located on a surface of a substrate, wherein each graphene nanoribbon of the ordered array of graphene nanoribbons has a width which is less than 10 nm 
     
     
         2 . The semiconductor structure of  claim 1 , wherein said width is from 4 nm to 9 nm. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein said ordered array of graphene nanoribbons is present as a hexagonal arrangement. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein said ordered array of graphene nanoribbons is present as a square arrangement. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein said ordered array of graphene nanoribbons is present as a triangular arrangement. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein each graphene nanoribbon of said plurality of graphene nanoribbons has a bottommost surface that is direct contact with a surface portion of said substrate, wherein said surface portion of said substrate is coplanar with other surface portions of said substrate not including said graphene nanoribbon. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein said substrate is a bulk semiconductor material. 
     
     
         8 . The semiconductor structure of  claim 6 , wherein said substrate includes a material stack of, from bottom to top, a semiconductor material and an insulator material. 
     
     
         9 . A semiconductor structure comprising:
 an ordered array of silicon carbide portions located on a surface of a substrate, wherein each silicon carbide portion of the ordered array of silicon carbide portions has a width which is less than 10 nm; and   a layer of graphene located on a topmost surface of each of said silicon carbide portions, wherein each layer of graphene has a width of less than 10 nm.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein each layer of graphene collectively provides a graphene lattice having an ordered lattice arrangement. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein said width of each layer of graphene is from 4 nm to 9 nm. 
     
     
         12 . The semiconductor structure of  claim 10 , wherein said lattice arrangement is a hexagonal arrangement. 
     
     
         13 . The semiconductor structure of  claim 10 , wherein said lattice arrangement is a square arrangement. 
     
     
         14 . The semiconductor structure of  claim 10 , wherein said lattice arrangement is a triangular arrangement. 
     
     
         15 . The semiconductor structure of  claim 9 , wherein each layer of graphene has a portion present on sidewall surfaces of each silicon carbide portion. 
     
     
         16 . The semiconductor structure of  claim 9 , wherein each layer of graphene is present only on a top surface of each of said silicon carbide portions 
     
     
         17 . The semiconductor structure of  claim 9 , wherein each silicon carbide portion of said plurality of silicon carbide portions has a bottommost surface that is direct contact with a surface portion of said substrate, wherein said surface portion of said substrate is vertically offset from other surface portions of said substrate not including said silicon carbide portions. 
     
     
         18 . The semiconductor structure of  claim 16 , wherein said substrate is sapphire.