Shared Virtual Memory

Abstract

Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

1 . A method providing:
 sharing memory semantics between a CPU and a GPU including allowing pointers to be passed and data structures to be shared as is between the CPU and GPU.   
     
     
         2 . The method claimed in  claim 1 , further comprising:
 sharing addresses between the CPU and GPU including allocating to a memory space a data structure that is shared as is between the CPU and GPU.   
     
     
         3 . The method claimed in  claim 1 , further comprising:
 sharing virtual addresses between the CPU and GPU but having the virtual addresses map to different physical addresses on the CPU and GPU.   
     
     
         4 . The method claimed in  claim 3 , wherein allocating to a memory space a data structure that is shared as is between the CPU and GPU further comprises using a malloc function that allocates data in the memory space. 
     
     
         5 . The method claimed in  claim 4  wherein allocating to a memory space a data structure that is shared between the CPU and GPU further comprises programmer annotation of static variables to have them allocated in the shared memory space. 
     
     
         6 . The method claimed in  claim 1  further comprising:
 migrating data shared in the memory space between the CPU and GPU memory on demand as it gets used by either the CPU or GPU. 
 
     
     
         7 . The method claimed in  claim 1 , further comprising
 partitioning address space into a shared address space between the CPU and GPU, and a remaining address space that is private to the CPU or GPU; and   allocating default data to the private space, wherein the default data is not visible to the other side.   
     
     
         8 . The method claimed in  claim 7 , wherein the representation of pointers does not change between shared and private spaces. 
     
     
         9 . The method claimed in  claim 7 , further comprising:
 the CPU or GPU specifying that it owns a particular chunk of addresses within the shared virtual address space.   
     
     
         10 . The method claimed in  claim 7 , wherein the CPU or GPU specifying that it owns a particular chunk of addresses within the shared virtual address space further comprises:
 when an address range in the shared virtual address is owned by the CPU, the CPU knows that the GPU cannot access those addresses and does not need to maintain coherence of those addresses with the GPU; and   when the CPU owned address is accessed by the GPU, the address becomes un-owned.   
     
     
         11 . The method claimed in  claim 1 , further comprising:
 determining if the CPU and GPU have different page tables and different virtual to physical memory translations; and   in response to different page tables and different virtual to physical memory translations, synchronizing the contents of virtual address between the CPU and GPU and the contents of different physical addresses.   
     
     
         12 . The method claimed in  claim 11 , wherein in response to different page tables and different virtual to physical memory translations, synchronizing the contents of virtual address between the CPU and GPU and the contents of different physical addresses further comprises:
 during initialization, mapping a portion of the PCI aperture that is accessible to both the CPU and GPU into the user space of an application and instantiating the user space with a task queue, a message queue, and copy buffers;   for copying pages from the CPU to the GPU, copying pages from the CPU address space into the PCI aperture and having the GPU access the pages from the PCI aperture into its address space; and   for copying pages from the GPU to the CPU, copying pages from the GPU address space into the PCI aperture and having the CPU access the pages from the PCI aperture into its address space.   
     
     
         13 . The method claimed in  claim 12 , wherein the PCI aperture may be mapped into the user space of the applications thus enabling user level CPU and GPU communication. 
     
     
         14 . The method claimed in  claim 13 , further comprising:
 placing a directory in the PCI aperture that contains metadata about the pages in the shared address region, wherein the metadata indicates whether the CPU or GPU holds the home for the page, contains a version number that tracks the number of updates to the page, and mutexes that are acquired before updating the page.   
     
     
         15 . The method claimed in  claim 14 , wherein the directory may be indexed by the virtual address of a page. 
     
     
         16 . The method claimed in  claim 1 , wherein the GPU comprises a discrete or integrated device or a combination of multiple GPUs in different configurations. 
     
     
         17 . The method claimed in  claim 1 , further comprising
 sharing memory semantics uniformly for multiple graphics cards and hybrid graphics systems.   
     
     
         18 . A shared memory wherein data structures are shared between a CPU and GPU, and pointers may be passed from one side to the other as is without requiring any marshalling. 
     
     
         19 . The shared memory claimed in  claim 18 , wherein a scene graph resides in the shared memory and can be accessed both by the CPU and GPU. 
     
     
         20 . The shared memory claimed in  claim 18 , wherein the shared memory is implemented with different operating systems running on the CPU and GPU. 
     
     
         21 . The shared memory claimed in  claim 18 , wherein the shared memory is implemented with the GPU attached as a discrete device to the CPU. 
     
     
         22 . The shared memory claimed in  claim 18 , wherein the shared memory is implemented in an integrated CPU-GPU platform. 
     
     
         23 . A computer readable medium storing instructions that, if executed, enable a processor-based system to:
 share memory semantics between a CPU and a GPU including allowing pointers to be passed and data structures to be shared as is between the CPU and GPU.   
     
     
         24 . The computer readable medium claimed in  claim 23 , further storing instructions to:
 share addresses between the CPU and GPU including allocating to a memory space a data structure that is shared as is between the CPU and GPU.   
     
     
         25 . The computer readable medium claimed in  claim 24 , further storing instructions to:
 share virtual addresses between the CPU and GPU and have the virtual addresses map to different physical addresses on the CPU and GPU.