Digital media processor

Abstract

Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 an embedded processor;   a programmable video processor; and   a 3-dimensional programmable graphics processing unit coupled to the embedded processor and video processor.   
     
     
         2 . The integrated circuit of  claim 1  further comprising:
 a motion estimation circuit coupled to the video processor and the graphics processing unit. 
 
     
     
         3 . The integrated circuit of  claim 1  further comprising:
 an Ethernet controller coupled to the graphics processor. 
 
     
     
         4 . The integrated circuit of  claim 1  further comprising:
 a wireless controller coupled to the graphics processor. 
 
     
     
         5 . The integrated circuit of  claim 1  wherein the integrated circuit is capable of simultaneously processing a plurality of video streams. 
     
     
         6 . The integrated circuit of  claim 1  wherein the integrated circuit is capable of decoding a video stream in the H.264 format. 
     
     
         7 . The integrated circuit of  claim 1  wherein the integrated circuit is capable of decoding a video stream in the WMV9 format. 
     
     
         8 . The integrated circuit of  claim 1  wherein the 3-dimensional programmable graphics processing unit includes a graphics pipeline that further includes a programmable shader. 
     
     
         9 . The integrated circuit of  claim 8  wherein the graphics pipeline further includes a vertex processor. 
     
     
         10 . An integrated circuit comprising:
 a digital input path;   an analog input path;   a multiplexer for selecting between the digital input path and analog input path;   a video processing circuit coupled to an output of the multiplexer, wherein the video processing circuit comprises:
 a first video processing sub-circuit; 
 a second video processing sub-circuit; and 
 a motion estimator coupled to the first and second video processor; and 
   a 3-dimensional graphics processing unit coupled to the video processing circuit,   wherein the first video processing sub-circuit and the graphics processing unit are programmable.   
     
     
         11 . The integrated circuit of  claim 10  further comprising:
 a first video output circuit; and 
 a second video output circuit. 
 
     
     
         12 . The integrated circuit of  claim 11  further comprising an audio processor. 
     
     
         13 . The integrated circuit of  claim 10  comprising:
 an embedded processor. 
 
     
     
         14 . The integrated circuit of  claim 13  wherein the embedded processor is an ARM processor core provided by ARM Holdings PLC. 
     
     
         15 . The integrated circuit of  claim 10  further comprising a plurality of input and output circuits configured to communicate with navigational, entertainment, safety, memory, and network devices. 
     
     
         16 . The integrated circuit of  claim 10  wherein the second video processing sub-circuit is programmable. 
     
     
         17 . The integrated circuit of  claim 16  wherein the first and second video processing sub-circuits can process both integer and floating data point types. 
     
     
         18 . The integrated circuit of  claim 10  wherein the 3-dimensional programmable graphics processing unit includes a graphics pipeline that further includes a programmable shader. 
     
     
         19 . The integrated circuit of  claim 18  wherein the graphics pipeline further includes a vertex processor. 
     
     
         20 . An integrated circuit comprising:
 an embedded processor;   a video circuit comprising:
 a first programmable video processing sub-circuit; 
 a second video processing sub-circuit; and 
 a 3-dimensional programmable graphics processing unit; 
   a plurality of input and output circuits; and   a memory interface circuit coupled to the embedded processor.