Using Fast Anneal to Form Uniform Ni(Pt)Si(Ge) Contacts on SiGe Layer

Abstract

Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a cap layer-free method for forming a silicide is provided. The method includes the following steps. A semiconductor material selected from: silicon and silicon germanium is provided. At least one silicide metal is deposited on the semiconductor material. The semiconductor material and the at least one silicide metal are annealed at a temperature of from about 400° C. to about 800° C. for a duration of less than or equal to about 10 milliseconds to form the silicide. A FET device and a method for fabricating a FET device are also provided.

1 . A cap layer-free method for forming a silicide, the method comprising the steps of:
 providing a semiconductor material selected from the group consisting of: silicon and silicon germanium;   depositing at least one silicide metal on the semiconductor material;   annealing the semiconductor material and the at least one silicide metal to form the silicide using a one step anneal which comprises annealing the semiconductor material and the at least one silicide metal at a temperature of from about 400° C. to about 800° C. for a duration of less than or equal to about 10 milliseconds; and   removing any unreacted metal after the one step anneal has been performed.   
     
     
         2 . The method of  claim 1 , wherein the semiconductor material comprises in situ boron doped silicon germanium. 
     
     
         3 . The method of  claim 2 , wherein the semiconductor material comprises from about 10% germanium to about 50% germanium. 
     
     
         4 . The method of  claim 1 , wherein the semiconductor material comprises implantation or in situ doped silicon. 
     
     
         5 . The method of  claim 1 , further comprising the step of:
 performing a pre-silicide clean of the semiconductor material to remove native oxide.   
     
     
         6 . The method of  claim 1 , wherein the at least one silicide metal is selected from the group consisting of: nickel, platinum, titanium, tantalum, cobalt, tungsten and combinations comprising at least one of the foregoing metals. 
     
     
         7 . The method of  claim 1 , wherein the at least one silicide metal comprises nickel-platinum. 
     
     
         8 . The method of  claim 1 , wherein the at least one silicide metal is deposited on the semiconductor material by evaporation or sputtering. 
     
     
         9 . The method of  claim 1 , wherein the annealing step is performed for a duration of from about 1 microsecond to about 10 milliseconds. 
     
     
         10 . The method of  claim 1 , wherein the annealing step is performed using a flash annealing process. 
     
     
         11 . The method of  claim 1 , wherein the annealing step is performed using a laser annealing process. 
     
     
         12 . The method of  claim 1 , further comprising the step of:
 pre-heating the semiconductor material to a temperature of from about 150° C. to about 350° C. prior to performing the annealing step, wherein a bottom side of the semiconductor material is pre-heated and the annealing is performed on a top of the semiconductor material.   
     
     
         13 . (canceled) 
     
     
         14 . The method of  claim 1 , wherein the unreacted metal is removed using a wet etching process. 
     
     
         15 . A method for fabricating a field-effect transistor (FET) device, the method comprising the steps of:
 providing a silicon-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX);   forming at least one active area in the wafer;   forming a gate stack over a portion of the at least one active area which will serve as a channel of the device;   forming source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device comprise a semiconductor material selected from the group consisting of: silicon and silicon germanium;   depositing at least one silicide metal on the wafer;   annealing the semiconductor material and the at least one silicide metal to form silicide contacts to the source and drain regions of the device using a one step anneal which comprises annealing the semiconductor material and the at least one silicide metal at a temperature of from about 400° C. to about 800° C. for a duration of less than or equal to about 10 milliseconds; and   removing any unreacted metal after the one step anneal has been performed.   
     
     
         16 . The method of  claim 15 , wherein the at least one active areas are formed in the wafer using shallow trench isolation (STI). 
     
     
         17 . The method of  claim 15 , further comprising the step of:
 forming spacers on opposite side of the gate stack.   
     
     
         18 . The method of  claim 15 , wherein the semiconductor material comprises in situ boron doped silicon germanium. 
     
     
         19 . The method of  claim 18 , wherein the semiconductor material comprises from about 10% germanium to about 50% germanium. 
     
     
         20 . The method of  claim 15 , wherein the semiconductor material comprises implantation or in situ doped silicon. 
     
     
         21 . The method of  claim 15 , wherein the at least one silicide metal is selected from the group consisting of: nickel, platinum, titanium, tantalum, cobalt, tungsten and combinations comprising at least one of the foregoing metals. 
     
     
         22 . The method of  claim 15 , wherein the annealing step is performed for a duration of from about 1 microsecond to about 10 milliseconds. 
     
     
         23 . The method of  claim 15 , wherein the annealing step is performed using a flash annealing process or a laser annealing process. 
     
     
         24 . (canceled) 
     
     
         25 . The method of  claim 15 , wherein the unreacted metal is removed using a wet etching process.