Concurrent access to a memory pool shared between a block access device and a graph access device

Abstract

A graph access device and block access device can simultaneously access a memory pool shared between the devices. The memory pool may include one or more memory arrays accessed as a single logical memory. The block access device accesses the memory pool as a flat array of memory blocks, and the graph access device accesses the memory pool as hierarchical file system. The simultaneous access is accomplished by monitoring one or more memory block access operations performed by the block access device, while it is accessing the memory pool. The block access operations are translated into a graph data structure including a plurality of pointers mapping the memory pool to the hierarchical file system. A processor regulates access to the memory pool, and is configured to permit the graph access device to access the memory pool concurrently with the block access device, in accordance with the graph data structure.

What is claimed is: 
     
         1 . A method for a graph access device and a block access device to simultaneously access a memory pool shared between the devices, comprising:
 monitoring one or more memory block access operations performed by the block access device while accessing one or more memory locations in the memory pool;   modifying a graph data structure based on the memory block access operations, the graph data structure including a plurality of pointers mapping the memory pool to a hierarchical file system; and   the graph access device accessing data in the memory locations in the memory pool that are also accessible to the block access device, according to the graph data structure.   
     
     
         2 . The method of  claim 1 , wherein the memory pool is a single logical memory. 
     
     
         3 . The method of  claim 1 , wherein the memory pool is included in a peripheral device. 
     
     
         4 . The method of  claim 1 , wherein the memory pool is distributed among a plurality of separate networked devices. 
     
     
         5 . The method of  claim 1 , wherein the graph access device includes a wireless client configured to access the memory pool over a wireless link. 
     
     
         6 . The method of  claim 1 , wherein the block access device includes a USB host configured to access the memory pool over a USB connection. 
     
     
         7 . The method of  claim 1 , wherein the block access device provides a discrete start location memory address and a discrete end location memory address, each located in the memory pool, for accessing the memory pool during the memory block access operations. 
     
     
         8 . The method of  claim 1 , wherein monitoring includes:
 determining whether the block memory access operations are writing to memory locations in the memory pool storing the graph data structure; and   determining whether the block memory access operations are writing to memory locations in the memory pool storing data content.   
     
     
         9 . The method of  claim 8 , wherein translating includes updating the graph data structure based on the memory locations written to by the block access device during the block memory access operations. 
     
     
         10 . The method of  claim 1 , wherein modifying includes updating the graph data structure based on a count of block memory access operations accessing predetermined memory address locations in the memory pool. 
     
     
         11 . An apparatus, comprising:
 a memory pool shared between a graph access device and a block access device;   means for monitoring one or more memory block access operations performed by the block access device while accessing one or more memory locations in the memory pool;   means for modifying a graph data structure based on the memory block access operations, the graph data structure including a plurality of pointers mapping the memory pool to a hierarchical file system; and   means for the graph access device accessing data in the memory locations in the memory pool that are also accessible to the block access device, according to the graph data structure.   
     
     
         12 . A peripheral device, comprising:
 a memory shared between a graph access device and a block access device;   a first communication interface configured to communicate with the block access device;   a second communication interface configured to communicate with the graph access device;   a processor, operatively coupled to the memory, and the first and second communication interfaces, configured to:   monitor one or more memory block access operations performed by the block access device while accessing the memory;   modify a graph data structure based on the memory block access operations, the graph data structure including a plurality of pointers mapping the memory to a hierarchical file system; and   permit the graph access device to access data in the memory locations in the memory pool that are also accessible to the block access device, according to the graph data structure.   
     
     
         13 . The peripheral device of  claim 12 , wherein the memory is included in a memory pool that is distributed among the peripheral device and at least one other separate device. 
     
     
         14 . The peripheral device of  claim 12 , wherein the second communication interface is configured to communicate with a plurality of graph access devices and the memory is shared between the block access device and the plurality of graph access devices. 
     
     
         15 . The peripheral device of  claim 12 , wherein the processor is configured to encrypt content stored in the memory. 
     
     
         16 . The peripheral device of  claim 12 , wherein the processor is configured to transcode content stored in the memory. 
     
     
         17 . The peripheral device of  claim 12 , wherein the processor is configured to authenticate the block access device and grant access to the memory only to a properly authenticated block access device. 
     
     
         18 . The peripheral device of  claim 12 , wherein the processor is configured to authenticate the graph access device and grant access to the memory only to a properly authenticated graph access device. 
     
     
         19 . A non-transitory computer-readable medium embodying a set of instructions executable by one or more processors, comprising:
 code for monitoring one or more memory block access operations performed by the block access device while accessing the memory pool;   code for modifying a graph data structure based on the memory block access operations, the graph data structure including a plurality of pointers mapping the memory pool to a hierarchical file system; and   code for the graph access device accessing data in the memory locations in the memory pool that are also accessible to the block access device, according to the graph data structure.