Non-volatile memory devices having charge storage layers at intersecting locations of word lines and active region

Abstract

Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.

What is claimed is: 
     
         1 . A nonvolatile memory device comprising:
 a plurality of parallel active regions defined by a plurality of device isolation layers formed on a semiconductor substrate, each of the plurality of parallel active regions extending in a first direction and having a top surface and sidewalls;   a plurality of parallel word lines each extending in a second direction and overlapping each of the plurality of parallel active regions at respective locations; and   a plurality of charge storage layers each disposed at each of the respective locations between the plurality of parallel active regions and the plurality of parallel word lines,   wherein each of the plurality of charge storage layers at the respective locations has a first side and a second side each parallel to the second direction and each having a first length, and a third side and a fourth side each parallel to the first direction and each having a second length, wherein the first length is less than the second length.   
     
     
         2 . The device of  claim 1  wherein the respective locations are above the plurality of active regions and below the plurality of word lines. 
     
     
         3 . The device of  claim 1  wherein each of the plurality of charge storage layers overlap all portions of the plurality of parallel active regions at the respective locations. 
     
     
         4 . The device of  claim 3  wherein the plurality of parallel active regions are exposed through the plurality of charge storage layers thereon between the respective locations. 
     
     
         5 . The device of  claim 1  wherein the plurality of charge storage layers comprise nitride layers. 
     
     
         6 . The device of  claim 1  further comprising:
 a plurality of oxide layers in contact with the plurality of charge storage layers at the respective locations. 
 
     
     
         7 . A nonvolatile memory device comprising:
 a plurality of parallel active regions defined by a plurality of device isolation layers formed on a semiconductor substrate, each of the plurality of parallel active regions extending in a first direction and having a top surface and sidewalls;   a plurality of parallel word lines each extending in a second direction and overlapping each of the plurality of parallel active regions at respective locations; and   a plurality of charge storage layers each disposed at each the respective locations between the plurality of parallel active regions and the plurality of parallel word lines;   wherein the respective locations comprise first and second sides each parallel to the second direction and each having a first length, and comprising third and fourth sides each parallel to the first direction and each having a second length that is greater than the first length.   
     
     
         8 . The device of  claim 7  wherein the respective locations are above the plurality of active regions and below the plurality of word lines. 
     
     
         9 . The device of  claim 7  wherein each of the plurality of charge storage layers overlap all portions of the plurality of parallel active regions at the respective locations. 
     
     
         10 . The device of  claim 9  wherein the plurality of parallel active regions are exposed through the plurality of charge storage layers thereon between the respective locations. 
     
     
         11 . The device of  claim 7  wherein the charge storage layers comprise nitride layers. 
     
     
         12 . The device of  claim 7  further comprising:
 a plurality of oxide layers in contact with the plurality of charge storage layers at the respective locations. 
 
     
     
         13 . A method of forming a nonvolatile memory device comprising:
 Forming a plurality of parallel active regions defined by a plurality of device isolation layers formed on a semiconductor substrate, each of the plurality of parallel active regions extending in a first direction and having a top surface and sidewalls;   Forming a plurality of parallel word lines each extending in a second direction and overlapping each of the plurality of parallel active regions at respective locations; and   Forming a plurality of charge storage layers each disposed at each of the respective locations between the plurality of parallel active regions and the plurality of parallel word lines,   wherein each of the plurality of charge storage layers at the respective locations has a first side and a second side each parallel to the second direction and each having a first length, and a third side and a fourth side each parallel to the first direction and each having a second length, wherein the first length is less than the second length.