Semiconductor device and method of fabricating the same

Abstract

According to example embodiments, a semiconductor device may include a substrate having an upper surface defining a groove and an active region, a device isolation layer in the groove, and a contact structure on the active region. The device isolation exposes the active region and may have a top surface that is higher than a top surface of the active region. The contact structure may include a first portion filling a gap region delimited by a sidewall of the device isolation layer and the top surface of the active region, the contact structure may include and a second portion on the device isolation layer so the second portion overlaps with the device isolation layer in a plan view.

1 . A semiconductor device, comprising:
 a substrate having an upper surface,
 the upper surface of the substrate defining a groove and an active region; 
   a device isolation layer in the groove of the substrate, the device isolation layer exposing the active region and having a top surface that is higher than a top surface of the active region of the substrate; and   a contact structure on the active region of the substrate,
 the contact structure including a first portion that fills a gap region delimited by a sidewall of the device isolation layer and the top surface of the active region, and 
 the contact structure including a second portion on the device isolation layer so the second portion overlaps the device isolation layer in a plan view. 
   
     
     
         2 . The device of  claim 1 , wherein
 the first portion contacts the sidewall of the device isolation layer, and   the first portion contacts the top surface of the active region.   
     
     
         3 . The device of  claim 2 , wherein
 the active region includes a first active region in a cell array region of the substrate,   the first active region includes a first impurity region and a second impurity region, and   a bottom surface of the first portion covers an entire area of a top surface of the second impurity region in the first active region.   
     
     
         4 . The device of  claim 1 , further comprising:
 conductive lines on the substrate,   wherein the second portion is between the conductive lines, and   the first portion extends below the conductive lines.   
     
     
         5 . The device of  claim 1 , further comprising:
 a cell gate structure buried in the substrate,   wherein a portion of the gap region is delimited by a sidewall of the cell gate structure.   
     
     
         6 . The device of  claim 5 , wherein a sidewall of the first portion is in contact with the sidewall of the cell gate structure. 
     
     
         7 . The device of  claim 5 , wherein
 the active region comprises a first impurity region and a second impurity region,   the first impurity region and the second impurity region are at both sides of the cell gate structure, and   the contact structure is connected to the second impurity region.   
     
     
         8 . The device of  claim 7 , further comprising:
 a data storing element connected to the contact structure.   
     
     
         9 . The device of  claim 8 , wherein
 the data storing element comprises a lower electrode, an upper electrode and an insulating layer, and   the insulating layer is between the lower and upper electrodes.   
     
     
         10 . The device of  claim 7 , further comprising:
 conductive lines on the substrate, wherein   the conductive lines cross the cell gate structure, and   the first impurity region is connected to the conductive lines.   
     
     
         11 . The device of  claim 10 , wherein
 each of the conductive lines comprises a third portion and a fourth portion,   the third portion overlaps with the device isolation layer in a plan view,   the fourth portion extends from the third portion toward the substrate, and   the fourth portion fills a region delimited by the sidewall of the device isolation layer and a top surface of the first impurity region.   
     
     
         12 . The device of  claim 10 , further comprising:
 a first interlayered insulating pattern between the conductive lines,   the first interlayered insulating pattern delimiting the second portion along with the conductive lines; and an etch stop layer between the device isolation layer and the conductive lines,   the etch stop layer including a material having an etch selectivity with respect to the first interlayered insulating pattern.   
     
     
         13 . The device of  claim 5 , wherein
 the top surface of the device isolation layer defines a trench, and   the cell gate structure comprises,
 a gate insulating layer in the trench, 
 a gate conductive layer in the trench and on the gate insulating layer, and 
 a capping layer on top surfaces of the gate insulating layer and the gate conductive layer, the capping layer filling the trench. 
   
     
     
         14 . The device of  claim 13 , further comprising:
 a peripheral gate structure, wherein   the upper surface of the substrate includes a cell region and a peripheral circuit region,   the cell gate structure is on the cell region of the substrate,   the peripheral gate structure is on the peripheral circuit region of the substrate, and   the upper surface of the substrate in the peripheral circuit region is lower than an upper surface of the capping layer.   
     
     
         15 . The device of  claim 1 , wherein
 the contact structure further comprises a conductive etch stop layer between the first portion and the active region, and   the conductive etch stop layer extends along the sidewall of the device isolation layer.   
     
     
         16 . A semiconductor device, comprising:
 a substrate;   a device isolation layer on the substrate,
 the device isolation layer exposing an active region of a substrate; 
   conductive lines on the substrate; and   a contact structure provided between the conductive lines,
 the contact structure connected to the active region, and 
 the contact structure including a lower portion that extends below the conductive lines. 
   
     
     
         17 . The device of  claim 16 , wherein the lower portion of the contact structure fills a gap region delimited by a sidewall of the device isolation layer and a top surface of the active region. 
     
     
         18 . The device of  claim 16 , wherein
 the contact structure comprises an upper portion, and   the upper portion overlaps with the device isolation layer in a plan view.   
     
     
         19 . The device of  claim 16 , further comprising:
 a cell gate structure buried in the substrate,   wherein a portion of the gap region is delimited by a sidewall of the cell gate structure.   
     
     
         20 . The device of  claim 19 , wherein
 the active region of the substrate includes a first impurity region and a second impurity region,   the first impurity region and the second impurity region are at both sides of the cell gate structure,   the contact structure is connected to the second impurity region, and   each of the conductive lines are connected to the first impurity region.   
     
     
         21 .- 40 . (canceled) 
     
     
         41 . A semiconductor device, comprising:
 a substrate having an upper surface,
 the upper surface of the substrate defining first active regions that protrude from the substrate and are separated by a groove, 
 each one of the first active regions including a first impurity region between a pair of second impurity regions; and 
   a plurality of contact structures that are spaced apart from each other,
 the plurality of contact structures each including a first portion on a corresponding one of the second impurity regions and a second portion that extends vertically from a part of an upper surface of the first portion, 
 each second portion including a lower surface that partially overlaps the groove in a plan view. 
   
     
     
         42 . The semiconductor device of  claim 41 , further comprising:
 a device isolation layer in the groove, wherein   the device isolation layer exposes the first active regions,   the device isolation includes a top surface that is higher than a top surface of the first active regions.   
     
     
         43 . The semiconductor device of  claim 42 , further comprising:
 a plurality of bit lines that are spaced apart from each other on the substrate, wherein the bit lines extend in a first direction, and   each one of the bit lines is electrically connected to the first impurity region and electrically isolated from the second impurity regions of at least two adjacent first active regions.   
     
     
         44 . The semiconductor device of  claim 43 , further comprising:
 a plurality of word line structures embedded in the device isolation layer, wherein   the plurality of word line structures extend in a second direction crossing the first direction.   
     
     
         45 . The semiconductor device of  claim 41 , further comprising:
 a peripheral gate structure, wherein   the substrate includes a cell array region and a peripheral circuit region,   the first active regions are in the cell array region of the substrate,   the upper surface of the substrate further defines a second active region in the peripheral circuit region of the substrate,   the second active region is spaced apart from the first active regions, and   the peripheral gate structure is on the second active region.