Fault Tolerant Integrated Circuit Architecture

Abstract

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

It is claimed: 
     
         1 . An apparatus comprising:
 a plurality of circuit arrays, each circuit array of the plurality of circuit arrays comprising:   a plurality of composite circuit elements, each composite circuit element comprising an element interface and a circuit element of a plurality of different circuit element types, each element interface comprising an element controller coupled to a circuit element; a plurality of input queues to store input data for the circuit element; a plurality of output queues to store data output from the circuit element; and one or more registers to store one or more designations of either or both a data input source or a data output destination;   at least one data queue to store a data word for transfer between adjacent circuit arrays of the plurality of circuit arrays; and   a full interconnect bus coupling the plurality of data output queues to the plurality of input queues and to the at least one data queue for a plurality of configurable data links, a first composite circuit element of the plurality of composite circuit elements having a first configurable data link of the plurality of configurable data links to a second composite circuit element of the plurality of composite circuit elements for performance of a first data operation and a second configurable data link of the plurality of configurable data links to a third composite circuit element of the plurality of composite circuit elements for performance of the first data operation or performance of a second data operation.   
     
     
         2 . The apparatus of  claim 1 , wherein the plurality of circuit element types comprises at least one of the following circuit element types: a plurality of configurable element types, a memory element type, a plurality of communication element types; and a plurality of non-configurable element types. 
     
     
         3 . The apparatus of  claim 1 , wherein the first configurable data link and the second configurable data link are configured during a boot process prior to run time, or in a binding process substantially at or during run-time, or during execution of an executable program. 
     
     
         4 . The apparatus of  claim 1 , further comprising:
 a sequential processor;   a configuration and control bus coupled to the sequential processor and to the plurality of circuit arrays.   
     
     
         5 . The apparatus of  claim 4 , wherein the first composite circuit element is configurable to perform a first function, the second composite circuit element is configurable to perform a second function, and the third composite circuit element is configurable to perform the second function and a third function. 
     
     
         6 . The apparatus of  claim 5 , wherein the sequential processor is to provide for configuring the third composite circuit element for the second function and configuring the second data link in response to an unavailability of the second composite circuit element. 
     
     
         7 . The apparatus of  claim 6 , wherein the second composite circuit element is unavailable due to a detected fault or to performance of another function having a higher priority than the second function. 
     
     
         8 . The apparatus of  claim 1 , wherein the one or more registers of each element interface further store at least one configuration of the corresponding circuit element. 
     
     
         9 . The apparatus of  claim 1 , wherein the one or more registers of each element interface further store a plurality of contexts, each context of the plurality of contexts specifying a configuration of a plurality of configurations of a circuit element. 
     
     
         10 . The apparatus of  claim 9 , wherein one or more input queues of the plurality of input queues of the first composite circuit element are configurable to receive data over the full interconnect bus from one or more output queues of the plurality of output queues of the second composite circuit element to provide the configurable first data link for a first context of the plurality of contexts of the first composite circuit element. 
     
     
         11 . The apparatus of  claim 9 , wherein one or more output queues of the plurality of output queues of the first composite circuit element are configurable to output data over the full interconnect bus to one or more input queues of the plurality of input queues of the second composite circuit element to provide the configurable first data link for a first context of the plurality of contexts of the first composite circuit element. 
     
     
         12 . The apparatus of  claim 9 , wherein the element controller further is to direct an execution of a first context of the plurality of contexts by the circuit element when all input queues of the plurality of input queues required by the first context have input data, when all output queues of the plurality of output queues required by the first context have room to accept output data, and when a status bit for the first context is set for execution. 
     
     
         13 . The apparatus of  claim 12 , wherein the element controller further is to arbitrate among a plurality of contexts which are ready for execution and to select a corresponding context for execution as a result of the arbitration, wherein the arbitration is selected from the group consisting of: round-robin, priority, most recently executed, least recently executed, scheduled execution; and combinations thereof. 
     
     
         14 . The apparatus of  claim 1 , further comprising:
 a plurality of data queues coupled to the full interconnect bus of a first circuit array of the plurality of circuit arrays, a first queue of the plurality of queues to transfer a first data word to an adjacent second circuit array of the plurality of circuit arrays and a second queue of the plurality of queues to receive a second data word from an adjacent third circuit array of the plurality of circuit arrays.   
     
     
         15 . An apparatus comprising:
 a sequential processor;   a configuration and control bus coupled to the sequential processor; and   a plurality of circuit arrays coupled to the configuration and control bus, each circuit array of the plurality of circuit arrays comprising:   a plurality of composite circuit elements, each composite circuit element comprising an element interface and a circuit element of a plurality of different circuit element types, each element interface comprising an element controller coupled to a circuit element; a plurality of input queues to store input data for the circuit element; a plurality of output queues to store data output from the circuit element; and one or more registers to store one or more designations of a data input source;   at least one data queue to store a data word for transfer between adjacent circuit arrays of the plurality of circuit arrays; and   a full interconnect bus coupling the plurality of data output queues to the plurality of input queues and to the at least one data queue;   wherein for each composite circuit element, one or more input queues of the plurality of input queues are configurable to receive data over the full interconnect bus from one or more output queues of the plurality of output queues of other composite circuit elements of the plurality of composite circuit elements or from the at least one data queue to provide a plurality of configurable data links between the plurality of composite circuit elements.   
     
     
         16 . The apparatus of  claim 15 , wherein the one or more registers of each element interface further store at least one configuration of the corresponding circuit element. 
     
     
         17 . The apparatus of  claim 15 , wherein the one or more registers of each element interface further store a plurality of contexts, each context of the plurality of contexts specifying a configuration of a plurality of configurations of a circuit element and designating one or more data input sources for at least one of the plurality of configurable data links of the plurality of configurable data links. 
     
     
         18 . The apparatus of  claim 15 , further comprising:
 a plurality of data queues coupled to the full interconnect bus of a first circuit array of the plurality of circuit arrays, a first queue of the plurality of queues to transfer a first data word to an adjacent second circuit array of the plurality of circuit arrays and a second queue of the plurality of queues to receive a second data word from an adjacent third circuit array of the plurality of circuit arrays.   
     
     
         19 . The apparatus of  claim 1 , wherein the plurality of configurable data links are configured during a boot process prior to run time, or in a binding process substantially at or during run-time, or during execution of an executable program. 
     
     
         20 . An apparatus comprising:
 a plurality of circuit arrays coupled to the configuration and control bus, each circuit array of the plurality of circuit arrays comprising:   a plurality of composite circuit elements, each composite circuit element comprising an element interface and a circuit element of a plurality of different circuit element types, each element interface comprising an element controller coupled to a circuit element; a plurality of input queues to store input data for the circuit element; a plurality of output queues to store data output from the circuit element; and one or more registers to store one or more designations of a data input source;   at least one data queue to store a data word for transfer between adjacent circuit arrays of the plurality of circuit arrays; and   a full interconnect bus coupling the plurality of data output queues to the plurality of input queues and to the at least one data queue;   wherein for each composite circuit element, one or more input queues of the plurality of input queues are configurable to receive data over the full interconnect bus from one or more output queues of the plurality of output queues of other composite circuit elements of the plurality of composite circuit elements or from the at least one data queue to provide a plurality of configurable data links between the plurality of composite circuit elements;   wherein at least one circuit array of the plurality of circuit arrays further comprises a memory composite circuit element.