Semiconductor memory device, memory controller and memory system having on die termination and on die termination controlling method

Abstract

A semiconductor memory device includes a first memory chip including a first on die termination (ODT) unit electrically connected to a first pad, the first pad being connected to a first terminal to receive a first signal, and a second memory chip including a second ODT unit electrically connected to a second pad, the second pad being connected to the first terminal to receive the first signal, the first ODT unit being configured to turn on/off according to a memory operation, the second ODT unit being configured to turn off regardless of the memory operation, and the first and second ODT units are switchable.

1 . A semiconductor memory device, comprising:
 a first memory chip including a first on die termination (ODT) unit electrically connected to a first pad, the first pad being connected to a first terminal to receive a first signal; and   a second memory chip including a second ODT unit electrically connected to a second pad, the second pad being connected to the first terminal to receive the first signal,   wherein the first ODT unit is configured to turn on/off according to a memory operation, the second ODT unit is configured to turn off regardless of the memory operation, and the first and second ODT are switchable.   
     
     
         2 .- 20 . (canceled)