Memory device and integrated circuit

Abstract

A memory device includes a nonvolatile memory, operated by using a plurality of voltages and configured to output stored repair information in response to a boot-up signal, a plurality of registers configured to store the repair information output from the nonvolatile memory, a plurality of memory banks configured to replace a normal cell with a redundancy cell using the repair information stored in registers corresponding to the plurality of memory banks among the plurality of registers, and a boot-up control circuit configured to activate the boot-up signal at a time of stabilization of the plurality of voltages.

What is claimed is: 
     
         1 . A memory device comprising:
 a nonvolatile memory, operated by using a plurality of voltages, and configured to output stored repair information in response to a boot-up signal;   a plurality of registers configured to store the repair information output from the nonvolatile memory;   a plurality of memory banks configured to replace a normal cell with a redundancy cell using the repair information stored in registers corresponding to the plurality of memory banks among the plurality of registers; and   a boot-up control circuit configured to activate the boo up signal at a time of stabilization of the plurality of voltages.   
     
     
         2 . The memory device of claim, wherein the boot-up control circuit comprises:
 a plurality of voltage detection units configured to detect voltage levels of the plurality of voltages, and to generate a plurality of detection signals which are activated when the voltage levels of the plurality of voltages reach respective target voltages; and   a signal generation unit configured to activate the boot-up signal when all the plurality of detection signals are activated.   
     
     
         3 . The memory device of  claim 1 , wherein the boot-up control circuit comprises:
 a plurality of voltage detection units configured to detect voltage levels of the plurality of voltages, and to generate a plurality of detection signals which are activated when the voltage levels of the plurality of voltages reach respective target voltages;   a plurality of delay units configured to delay the plurality of detection signals and generate a plurality of delayed detection signals; and   a signal generation unit configured to activate the boot-up signal when all the plurality of delayed detection signals are activated.   
     
     
         4 . The memory device of claim, wherein the boo up control circuit comprises:
 a clamp unit configured to transfer the plurality of voltages in response to a level of one of the plurality of voltages;   a plurality of voltage detection units configured to generate a plurality of detection signals which are activated when voltage levels of the plurality of voltages received from the clamp unit reach respective target voltages;   a plurality of delay units configured to delay the plurality of detection signals; and   a signal generation unit configured to activate the boot-up signal when all the plurality of detection signals delayed by the plurality of delay units are activated.   
     
     
         5 . The memory device of  claim 4 , wherein the one voltage is a voltage which is lastly stabilized among the plurality of voltages. 
     
     
         6 . The memory device of  claim 1 , wherein the boot-up control circuit comprises:
 a voltage detection unit configured to detect a level of one of the plurality of voltages, and to generate the boot-up signal which is activated when the one voltage reaches a target voltage.   
     
     
         7 . The memory device of  claim 1 , wherein the boot-up control circuit comprises:
 a voltage detection unit configured to detect a level of one of the plurality of voltages, and to generate a detection signal which is activated when the one voltage reaches a target voltage; and   a delay unit configured to delay the detection signal and generate the boot-up signal.   
     
     
         8 . The memory device of claim wherein the boot-up control circuit comprises:
 a clamp unit configured to transfer one voltage of the plurality of voltages in response to the one voltage;   a voltage detection unit configured to generate a detection signal which is activated when a voltage level of the voltage received through the clamp unit reaches a target voltage; and   a delay unit configured to delay the detection signal and generate the boot-up signal.   
     
     
         9 . The memory device of  claim 6 , wherein the one voltage is a voltage which is lastly stabilized among the plurality of voltages. 
     
     
         10 . The memory device of  claim 7 , wherein the one voltage is a voltage which is lastly stabilized among the plurality of voltages. 
     
     
         11 . The memory device of  claim 8 , wherein the one voltage is a voltage which is lastly stabilized among the plurality of voltages. 
     
     
         12 . The memory device of  claim 1 , wherein the plurality of voltages include a power supply voltage applied from an exterior of the memory device, a division voltage generated by dividing the power supply voltage, a high voltage generated by pumping the power supply voltage, and a negative voltage generated by pumping a ground voltage. 
     
     
         13 . The memory device of  claim 1 , wherein the nonvolatile memory includes one of an e-fuse array circuit, a NAND flash memory, a NOR flash memory, an EPROM, an EEPROM, a FRAM, and a MRAM. 
     
     
         14 . An integrated circuit comprising:
 a nonvolatile memory, operated by using a plurality of voltages and configured to output stored data in response to a boot-up signal;   a plurality of registers configured to store the data output from the nonvolatile memory;   a plurality of internal circuits configured to operate using the data stored in registers corresponding to the plurality of internal circuits among the plurality of registers; and   a boot-up control circuit configured to activate the boot-up signal at a time of stabilization of the plurality of voltages.   
     
     
         15 . The integrated circuit of  claim 14 , wherein the boot-up control circuit comprises:
 a plurality of voltage detection units configured to detect voltage levels of the plurality of voltages, and to generate a plurality of detection signals which are activated when the voltage levels of the plurality of voltages reach respective target voltages; and   a signal generation unit configured to activate the boot-up signal when all the plurality of detection signals are activated.   
     
     
         16 . The integrated circuit of  claim 14 , wherein the boot-up control circuit comprises:
 a plurality of voltage detection units configured to detect voltage levels of the plurality of voltages, and to generate a plurality of detection signals which are activated when the voltage levels of the plurality of voltages reach respective target voltages;   a plurality of delay units configured to delay the plurality of detection signals and generate a plurality of delayed detection signals; and   a signal generation unit configured to activate the boot-up signal when all the plurality of delayed detection signals are activated.   
     
     
         17 . The integrated circuit of  claim 14 , wherein the boot-up control circuit comprises:
 a clamp unit configured to transfer the plurality of voltages in response to a level of one of the plurality of voltages;   a plurality of voltage detection units configured to detect voltage levels of the plurality of voltages, and to generate a plurality of detection signals which are activated when the voltage levels of the plurality of voltages reach respective target voltages;   a plurality of delay units configured to delay the plurality of detection signals and generate a plurality of delayed detection signals; and   a signal generation unit configured to activate the boot-up signal when all the plurality of delayed detection signals are activated.   
     
     
         18 . The integrated circuit of clam  14 , wherein the boot-up control circuit comprises:
 a voltage detection unit configured to detect a level of one of the plurality of voltages and to generate the boot-up signal which is activated when the one voltage reaches a target voltage.   
     
     
         19 . The integrated circuit of  claim 14 , wherein the boot-up control circuit comprises:
 a voltage detection unit configured to detect a level of one of the plurality of voltages, and to generate a detection signal which is activated when the one voltage reaches a target voltage; and   a delay unit configured to delay the detection signal and generate the boot-up signal.   
     
     
         20 . The integrated circuit of  claim 14 , wherein the boot-up control circuit comprises:
 a clamp unit configured to transfer one voltage of the plurality of voltages in response to the one voltage;   a voltage detection unit configured to generate a detection signal which is activated when a voltage level of the voltage received through the clamp unit reaches a target voltage; and   a delay unit configured to delay the detection signal and generate the boot-up signal.