Semiconductor storage device and memory controller

Abstract

According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data.

What is claimed is: 
     
         1 . A semiconductor storage device comprising:
 a non-volatile semiconductor memory;   an encoding unit that performs an error correction coding process on data to be written on the non-volatile semiconductor memory to generate a parity;   a writing control unit that writes the data and the parity on the non-volatile semiconductor memory;   a decoding unit that performs an error correcting process based on the data and the parity read from the non-volatile semiconductor memory; and   a compaction processing unit that performs a compaction process of writing valid data of the data and the parity stored in a first region which is a region with a predetermined size in the non-volatile semiconductor memory on a second region, which is a region with a predetermined size other than the first region of the non-volatile semiconductor memory,   wherein the decoding unit includes
 a syndrome calculating unit that calculates a syndrome based on the data and the parity read from the non-volatile semiconductor memory, 
 an error position polynomial calculating unit that calculates an error position polynomial based on the syndrome and acquires the number of error bits based on the error position polynomial, 
 an error searching and correcting unit that acquires an error position based on the error position polynomial and performs error correction of the acquired error position, and 
   wherein at the time of performing the compaction process, the processes of the syndrome calculating unit and the error position polynomial calculating unit are performed based on the valid data, and the valid data is written on the second region without performing the process of the error searching and correcting unit, when the number of error bits acquired by the error position polynomial calculating unit is equal to or less than a first threshold value.   
     
     
         2 . The semiconductor storage device according to  claim 1 , wherein when the number of error bits acquired by the error position polynomial calculating unit is greater than the first threshold value, the process of the error searching and correcting unit is performed. 
     
     
         3 . The semiconductor storage device according to  claim 2 , wherein when the number of error bits acquired by the error position polynomial calculating unit is greater than the first threshold value, the error searching and correcting unit detects and corrects error positions corresponding to all of the bits of the number of error bits. 
     
     
         4 . The semiconductor storage device according to  claim 2 , wherein when the number of error bits acquired by the error position polynomial calculating unit is greater than the first threshold value, the error searching and correcting unit detects and corrects error positions corresponding to the number of correction bits less than the number of error bits. 
     
     
         5 . The semiconductor storage device according to  claim 2 , wherein when the number of error bits acquired by the error position polynomial calculating unit is greater than the first threshold value and is equal to or less than a second threshold value, the error searching and correcting unit detects and corrects error positions corresponding to the number of correction bits less than the number of error bits, and
 when the number of error bits is greater than the second threshold value, the error searching and correcting unit detects and corrects error positions corresponding to all of the bits of the number of error bits.   
     
     
         6 . The semiconductor storage device according to  claim 1 , wherein the first threshold value is determined based on a maximum correction capability of the decoding unit. 
     
     
         7 . The semiconductor storage device according to  claim 1 , wherein the first threshold value is determined based on a data length of data to be decoded. 
     
     
         8 . The semiconductor storage device according to  claim 1 , further comprising:
 a control unit that records the number of erasures for each region with the predetermined size,   wherein the first threshold value is determined based on the number of erasures of the second region.   
     
     
         9 . The semiconductor storage device according to  claim 1 , further comprising:
 a control unit that records a maximum number of error bits for each region with the predetermined size,   wherein the first threshold value is determined based on the maximum number of error bits of the second region.   
     
     
         10 . The semiconductor storage device according to  claim 1 , further comprising:
 a control unit that manages a program required time for each region with the predetermined size,   wherein the first threshold value is determined based on the program required time of the second region.   
     
     
         11 . The semiconductor storage device according to  claim 1 , further comprising:
 a control unit that manages an erase required time for each region with the predetermined size,   wherein the first threshold value is determined based on the erase required time of the second region.   
     
     
         12 . The semiconductor storage device according to  claim 4 ,
 wherein the correction bits are determined as a value obtained by subtracting a remaining number of bits from the number of error bits, and   the first threshold value and the remaining number of bits are determined based on a maximum correction capability of the decoding unit.   
     
     
         13 . The semiconductor storage device according to  claim 4 ,
 wherein the correction bits are determined as a value obtained by subtracting a remaining number of bits from the number of error bits, and   the first threshold value and the remaining number of bits are determined based on a data length of data to be decoded.   
     
     
         14 . The semiconductor storage device according to  claim 4 , further comprising:
 a control unit that records the number of erasures for each region with the predetermined size,   wherein the correction bits are determined as a value obtained by subtracting a remaining number of bits from the number of error bits, and   the first threshold value and the remaining number of bits are determined based on the number of erasures of the second region.   
     
     
         15 . The semiconductor storage device according to  claim 4 , further comprising:
 a control unit that records a maximum number of error bits for each region with the predetermined size,   wherein the correction bits are determined as a value obtained by subtracting a remaining number of bits from the number of error bits, and   the first threshold value and the remaining number of bits are determined based on the maximum number of error bits of the second region.   
     
     
         16 . The semiconductor storage device according to  claim 4 , further comprising:
 a control unit that manages a program required time for each region with the predetermined size,   wherein the correction bits are determined as a value obtained by subtracting a remaining number of bits from the number of error bits, and   the first threshold value and the remaining number of bits are determined based on the program required time of the second region.   
     
     
         17 . The semiconductor storage device according to  claim 4 , further comprising:
 a control unit that manages an erase required time for each region with the predetermined size,   wherein the correction bits are determined as a value obtained by subtracting a remaining number of bits from the number of error bits, and   the first threshold value and the remaining number of bits are determined based on the erase required time of the second region.   
     
     
         18 . A memory controller that controls a non-volatile semiconductor memory, the memory controller comprising:
 an encoding unit that performs an error correction coding process on data to be written on the non-volatile semiconductor memory to generate a parity;   a writing control unit that writes the data and the parity on the non-volatile semiconductor memory;   a decoding unit that performs an error correcting process based on the data and the parity read from the non-volatile semiconductor memory; and   a compaction processing unit that performs a compaction process of writing valid data of the data and the parity stored in a first region which is a region with a predetermined size in the non-volatile semiconductor memory on a second region which is a region with a predetermined size other than the first region of the non-volatile semiconductor memory,   wherein at the time of performing the compaction process, when the number of error bits of the valid data is acquired and the number of error bits is equal to or less than a first threshold value, the error correcting process is not performed at least partially, and   when the number of error bits is greater than the first threshold value, the error correcting process is performed.   
     
     
         19 . A memory controller that controls a non-volatile semiconductor memory, the memory controller comprising:
 an encoding unit that performs an error correction coding process on data to be written on the non-volatile semiconductor memory to generate a parity;   a writing control unit that writes the data and the parity on the non-volatile semiconductor memory;   a decoding unit that performs an error correcting process based on the data and the parity read from the non-volatile semiconductor memory; and   a compaction processing unit that performs a compaction process of writing valid data of the data and the parity stored in a first region which is a region with a predetermined size in the non-volatile semiconductor memory on a second region which is a region with a predetermined size other than the first region of the non-volatile semiconductor memory,   wherein the decoding unit includes
 a syndrome calculating unit that calculates a syndrome based on the data and the parity read from the non-volatile semiconductor memory, 
 an error position polynomial calculating unit that calculates an error position polynomial based on the syndrome and acquires the number of error bits based on the error position polynomial, 
 an error searching and correcting unit that acquires an error position based on the error position polynomial and performs error correction of the acquired error position, and 
   wherein at the time of performing the compaction process, the processes of the syndrome calculating unit and the error position polynomial calculating unit are performed based on the valid data, and the valid data is written on the second region without performing the process of the error searching and correcting unit, when the number of error bits acquired by the error position polynomial calculating unit is equal to or less than a first threshold value.