Semiconductor memory array structure

Abstract

A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.

1 . A memory array, comprising:
 a plurality of rhomboid-shaped active area (AA) regions in a substrate, each of the rhomboid-shaped AA regions having a pair of longer sides and a pair of shorter sides;   a first shallow trench isolation (STI) structure extending along a first direction on the longer sides of the rhomboid-shaped AA region, wherein the first STI structure has a depth d1; and   a second STI structure extending along a second direction on the shorter sides of the rhomboid-shaped AA region, wherein the second STI structure has two depths: d2 and d3, the depth d3 is the depth of overlapping regions where the first STI structure intersects the second STI structure, the depths d1, d2 and d3 are different, and the depths d1 and d2 are shallower than d3.   
     
     
         2 . (canceled) 
     
     
         3 . The memory array according to  claim 1  wherein the second STI structure has the depth d2 in a sub-region located between the overlapping regions. 
     
     
         4 . The memory array according to  claim 1  wherein the depth d1 and the depth d2 range between 2300˜2600 angstroms. 
     
     
         5 . The memory array according to  claim 1  wherein the depth d3 ranges between 2600-2800 angstroms. 
     
     
         6 . The memory array according to  claim 1  wherein the substrate is a silicon substrate. 
     
     
         7 . The memory array according to  claim 1  wherein the first direction is not perpendicular to the second direction.