Bandwidth efficient instruction-driven multiplication engine

Abstract

Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of to the second operands from the compute register file to respective multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the local operand register to respective multipliers, to supply the second operands from the compute register file to respective multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein one or more of the first operands in the local operand register are reused by the multipliers in two or more multiplication operations.

What is claimed is: 
     
         1 - 17 . (canceled) 
     
     
         18 . A digital processor for performing a finite impulse response (FIR) filter operation on data numbers comprising:
 a plurality of multipliers, each receiving a first operand and a second operand, wherein the first operands correspond to the data numbers, and the second operands correspond to coefficients for the FIR filter operation;   a local operand register having a plurality of locations to hold the first operands corresponding to a subset of the data numbers for the plurality of multipliers, wherein the plurality of locations correspond to respective ones of the multipliers;   a control unit responsive to a digital processor instruction to supply the first operands from the plurality of locations the local operand register to respective ones of the multipliers, to supply the second operands from a compute register file to respective ones of the multipliers and to multiply the first operands by the respective second operands in the respective multipliers,   wherein the control unit, upon detecting a first multiplication operation being executed by a first multiplier:
 (1) causes the first operands corresponding to the subset of the data numbers to shift in the local operand register by a number of bits equal to a width of the first operands to respective next locations in the plurality of locations of the local operand register; 
 (2) if available, loads a next data number from the compute register file to the local operand register; and 
 (3) supplies the shifted first operands and the next data number to the plurality of multipliers, thereby causing one or more of the first operands in the local operand register used by the first multiplier in the first multiplication operation to be reused by the at least one subsequent multiplier in at least one subsequent multiplication operation, and enabling two or more multiply instructions to be executed without reloading the local operand register with a complete set of new operands after each multiplication operation. 
   
     
     
         19 . The digital processor of  claim 18 , wherein the compute register file stores the data numbers and the coefficients for the FIR filter operation. 
     
     
         20 . The digital processor of  claim 19 , further comprising:
 a first operand bus coupled to the local operand register to supply the first operands corresponding to the subset of data numbers from the compute register file to the local operand register.   
     
     
         21 . The digital processor of  claim 19 , further comprising:
 a second operand bus coupled to the plurality of multipliers to supply the second operands corresponding to one of the coefficients for the FIR filter operation from the compute register file to each of the multipliers.   
     
     
         22 . The digital processor of  claim 18 , wherein a number of taps for the FIR filter correspond to a number of the plurality of multipliers used in the multiplication operation. 
     
     
         23 . The digital processor of  claim 18 , wherein each successive multiplication operations multiplies a shifted window of data numbers with one of the coefficients for the FIR filter. 
     
     
         24 . The digital processor of  claim 18 , wherein the first operands corresponding to the subset of the data numbers shift to the right by the number of bits equal to the number of bits for each data number, and the next data number is loaded to a most significant bit location of the local operand register. 
     
     
         25 . The digital processor of  claim 21 , wherein the second operand bus is configured to broadcast one of the coefficients of the FIR filter from the compute register file to each of the multipliers. 
     
     
         26 . The digital processor of  claim 21 , wherein the control unit, upon detecting the first multiplication operation being executed, further causes the second operand bus to broadcast a next one of the coefficients of the FIR filter from the compute register file to each of the multipliers. 
     
     
         27 . The digital processor for  claim 18 , wherein each of the first operands comprises a data number having 16-bits. 
     
     
         28 . The digital processor for  claim 27 , wherein the data number comprises 16 bits and the data number is a complex number having 8-bits real and 8-bits imaginary. 
     
     
         29 . The digital processor for  claim 27 , wherein the first operands corresponding to the subset of the data numbers shift by 16-bits to the right in the local operand register respective next locations in the plurality of locations of the local operand register. 
     
     
         30 . A method for performing in a digital processor a finite impulse response (FIR) filter operation on data numbers, comprising:
 loading first operands for a plurality of multipliers from a compute register file to a plurality of locations in a local operand register using a first operand bus, wherein a plurality of locations are configured to hold the first operands for respective ones of the multipliers, and the first operands stored in the local operand register correspond to a subset of the data numbers,   supplying second operands for the plurality of multipliers from the compute register file to respective ones of the plurality of multipliers using a second operand bus, wherein the second operands correspond to coefficients for the FIR filter operation;   controlling operation of the multipliers and the local operand register in response to a digital processor instruction by supplying the first operands corresponding to the subset of the data numbers from the plurality of locations of the local operand register to respective ones of the multipliers, supplying the second operands from the compute register file to respective ones of the multipliers on the second operand bus and multiplying the first operands by the respective second operands in respective ones of the multipliers;   shifting the local operand register corresponding to the subset of the data numbers a number of bits equal to a width of the first operands to respective next locations in the plurality of locations of the local operand register upon detecting a first multiplication operation being executed by a first multiplier;   loading if available, a next data number to the local operand register; and   supplying the shifted first operands and the next data number to the plurality of multipliers, thereby causing one or more of the first operands in the local operand register used by the first multiplier in the first multiplication operation to be reused by the at least one subsequent multiplier in at least one subsequent multiplication operation and enabling two or more multiply instructions to be executed without reloading the local operand register with a complete set of new operands after each multiplication operation.   
     
     
         31 . The method of  claim 30 , wherein the steps for shifting the local operand register corresponding to the subset of data numbers causes successive multiplication operations to multiply a shifted window of data numbers with one of the coefficients for the FIR filter. 
     
     
         32 . The method of  claim 30 , wherein the first operands corresponding to the subset of the data numbers in the local operand register are shifted to the right by the width of each data number, and the next data number is loaded to a most significant bit location of the local operand register. 
     
     
         33 . The method of  claim 30 , wherein the second operand bus is configured to broadcast one of the coefficients of the FIR filter from the compute register file to each of the multipliers. 
     
     
         34 . The method of  claim 30 , wherein the controlling operation of the multipliers comprises broadcasting a next one of the coefficients of the FIR filter from the compute register file to each of the multipliers in response to the digital processor instruction. 
     
     
         35 . The method of  claim 30 , wherein each of the first operands comprises a data number having 16-bits. 
     
     
         36 . The method of  claim 35 , wherein the data number comprises 16 bits and the data number is a complex number having 8-bits real and 8-bits imaginary. 
     
     
         37 . The method of  claim 35 , wherein the first operands corresponding to the subset of the data numbers in the local operand register are shifted by 16-bits to the right in the local operand register respective next locations in the plurality of locations of the local operand register.