Semiconductor memory device, memory controller, and data processing system including these

Abstract

In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened.

What is claimed is: 
     
         1 . A memory controller that controls a semiconductor memory device including an interface chip and a plurality of core chips, the memory controller comprising:
 a first circuit that issues a refresh command at a plurality of times during a predetermined period; and   a second circuit that issues address information that selects the core chips along with the refresh command.   
     
     
         2 . The memory controller as claimed in  claim 1 , further comprising
 a plurality of memory cells provided in each of the core chips are classified into a plurality of independent regions that are mutually non-exclusively controlled, wherein   the memory controller does not issue a bank address that selects one of the independent regions along with the refresh command.   
     
     
         3 . The memory controller as claimed in  claim 1 , further comprising a third circuit that sets the semiconductor memory device in one of a first operation mode and a second operation mode, wherein
 a number of times in which the first circuit issues the refresh command during the predetermined period on the semiconductor memory device is set in the first operation mode is greater than a number of times in which the first circuit issues the refresh command during the predetermined period on the semiconductor memory device is set in the second operation mode.   
     
     
         4 . The memory controller as claimed in  claim 3 , wherein the number of times in which the first circuit issues the refresh command during the predetermined period on the semiconductor memory devise is set in the first operation mode is a power of two of the number of times in which the first circuit issues the refresh command during the predetermined period on the semiconductor memory device is set in the second operation mode. 
     
     
         5 . The memory controller as claimed in  claim 3 , wherein on the semiconductor memory device is set in the second operation mode, the memory controller does not supply the address information that selects the core chip along with the refresh command. 
     
     
         6 . The memory controller as claimed in  claim 2 , further comprising a third circuit that sets the semiconductor memory device in one of a first operation mode and a second operation mode, wherein a number of times in which the first circuit issues the refresh command during the predetermined period on the semiconductor memory device is set in the first operation mode is greater than a number of times in which the first circuit issues the refresh command during the predetermined period on the semiconductor memory device is set in the second operation mode. 
     
     
         7 . The memory controller as claimed in  claim 6 , wherein the number of times in which the first circuit issues the refresh command during the predetermined period on the semiconductor memory device is set in the first operation mode is a power of two of the number of times in which the first circuit issues the refresh command during the predetermined period on the semiconductor memory device is set in the second operation mode. 
     
     
         8 . The memory controller as claimed in  claim 6 , wherein when the semiconductor memory device is set in the second operation mode, the memory controller does not supply the address information that selects the core chip along with the refresh command.