Non-volatile memory devices and methods of manufacturing the same

Abstract

A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

What is claimed is: 
     
         1 . A method of manufacturing a memory device, comprising:
 providing a semiconductor substrate having a plurality of recesses and protrusions;   forming a dielectric layer along a surface profile of the recesses and the protrusions; and   forming a conductive pattern on the dielectric layer to have a first pattern and a second pattern, the first pattern being formed on the dielectric layer at a first temperature and the second pattern being formed on the first pattern at a second temperature lower than the first temperature.   
     
     
         2 . The method of  claim 1 , wherein forming the conductive pattern on the dielectric layer includes:
 forming a first preliminary conductive layer on the dielectric layer along the surface profile thereof;   forming a second preliminary conductive layer on the first preliminary layer, the second preliminary conductive layer being doped with impurities;   performing a first heating process at the second temperature, thereby forming the second preliminary layer into a second conductive layer;   performing a second heating process at the first temperature, thereby forming the first preliminary layer into a first conductive layer; and   sequentially patterning the second conductive layer and the first conductive layer, thereby forming the second pattern and the first pattern of the conductive pattern.   
     
     
         3 . The method of  claim 2 , wherein the first and the second preliminary layers include amorphous silicon and the second temperature is in a range of 500° C. to 700° C. while the first temperature is in a range of 750° C. to 800° C. 
     
     
         4 . The method of  claim 2 , wherein forming the second preliminary conductive layer doped with the impurities includes a step of implanting impurities into the second preliminary conductive layer to such a depth that the first preliminary conductive layer is not doped with the impurities. 
     
     
         5 . The method of  claim 4 , wherein the impurities includes any one material selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), phosphorus (P), boron (B) and compounds thereof. 
     
     
         6 . A method of manufacturing a non-volatile memory device, comprising:
 forming a first dielectric pattern on an active region of the substrate in a first direction, the active region being defined by a device isolation pattern of a field region of the substrate;   forming a first gate pattern on the first dielectric pattern into a plurality of first gate lines extending in the first direction such that the first gate lines are spaced apart and the device isolation pattern is exposed through a recess between the neighboring first gate lines;   forming a second dielectric pattern on upper and side surfaces of the first gate pattern and on the exposed device isolation pattern along a surface profile of the first gate pattern; and   forming a second gate pattern on the second dialectic pattern into a plurality of second gate lines extending in a second direction perpendicular to the first direction, the second gate pattern including a first conductive pattern arranged on the second dielectric pattern along the surface profile of the first gate pattern and a second conductive pattern arranged on the first conductive pattern to fill up the recess.   
     
     
         7 . The method of  claim 6 , wherein forming the second gate pattern includes:
 forming a first preliminary conductive layer undoped with impurities on the second dielectric pattern along a surface profile of the first gate pattern;   forming a second preliminary conductive layer doped with impurities on the first preliminary conductive layer to a sufficient thickness to fill up the recess;   performing a first heating process, thereby forming a second conductive layer doped with impurities from the second preliminary conductive layer;   performing a second heating process to the first preliminary conductive layer at a temperature higher than that of the first heating process, thereby forming a first conductive layer undoped with impurities from the first preliminary conductive layer; and   sequentially patterning the second conductive layer and the first conductive layer, thereby forming the second conductive pattern and the first conductive pattern of the conductive pattern.   
     
     
         8 . The method of  claim 7 , wherein forming the first preliminary conductive layer includes:
 performing a first cleaning process to a surface of the second dielectric pattern; and   forming a first amorphous silicon layer on the second dielectric layer by a first deposition process using one of di-silane (Si2H6) gases and tri-silane (si3H8) gases as a source gas.   
     
     
         9 . The method of  claim 8 , wherein forming the second preliminary conductive layer includes:
 forming a second amorphous silicon layer on the first amorphous silicon layer by a second deposition process using monosilane (SiH4) gases as a source gas; and   doping impurities into the second amorphous silicon layer.   
     
     
         10 . The method of  claim 9 , wherein doping impurities into the second amorphous silicon layer is performed by one of an ion implantation process and a diffusion process, and the impurities includes any one material selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), phosphorus (P), boron (B) and compounds thereof. 
     
     
         11 . The method of  claim 9 , wherein the first and the second preliminary conductive layers are formed in different process chambers. 
     
     
         12 . The method of  claim 11 , wherein a second cleaning process is further performed on a surface of the first preliminary conductive layer, so that a native oxide layer is removed from the first preliminary conductive layer prior to the step of forming the second preliminary conductive layer. 
     
     
         13 . The method of  claim 12 , wherein the second cleaning process includes a wet cleaning process using ozone (O3) water, ammonium hydroxide and an aqueous HF solution as a cleaning solution. 
     
     
         14 . The method of  claim 7 , wherein the first heating process is performed at a temperature of about 500° C. to about 700° C. and the second heating process is performed at a temperature of about 750° C. to about 850° C. 
     
     
         15 . The method of  claim 14 , wherein the first and the second heating processes are consecutively performed in an inactive gas atmosphere. 
     
     
         16 . The method of  claim 7 , wherein the first conductive layer and the first conductive layer are sequentially patterned in the second direction, thereby forming the first conductive pattern and the second conductive pattern sequentially stacked on the second dielectric pattern. 
     
     
         17 . The method of  claim 16 , further comprising:
 forming a third conductive layer on the second conductive layer; and   sequentially patterning the third, the second and the first conductive layers in the second direction, thereby forming a third conductive pattern stacked on the second conductive pattern.   
     
     
         18 . The method of  claim 17 , wherein the third conductive layer includes a conductive material selected from the group consisting of tungsten (W), tantalum (Ta) and titanium (Ti) and compounds thereof. 
     
     
         19 . The method of  claim 6 , wherein the first gate pattern is protruded from a surface of the device isolation pattern to a protrusion height of about 60 nm to about 75 nm and the width of the recess is in a range of about 20 nm to about 25 nm. 
     
     
         20 . The method of  claim 19 , wherein the first conductive pattern is formed to a thickness of about 10 nm from a surface of the second dielectric pattern.