Fabricating a semiconductor die having coefficient of thermal expansion graded layer

Abstract

A method of fabricating a semiconductor die includes circuit elements configured to provide a circuit function. A substrate including a bottomside and a topside is provided. At least one multi-layer structure is formed. The forming is done by depositing a coefficient of thermal expansion (CTE) graded layer comprising at least a dielectric portion on a first material having a first CTE to provide a first side facing said first material and a second side opposite the first side. The depositing includes flowing a first reactive component and at least a second reactive component. A gas flow ratio of the first reactive component relative to the second reactive component is automatically changed during a deposition time to provide a non-constant composition profile which has a graded CTE that increases from the first side to the second side. A metal layer comprising a second material having a second CTE is formed on the second side. The second CTE is higher than the first CTE.

We claim: 
     
         1 - 13 . (canceled) 
     
     
         14 . A method of fabricating a semiconductor die including circuit elements configured to provide a circuit function, comprising:
 providing a substrate including a bottomside and a topside, and   forming at least one multi-layer structure, including:
 depositing a coefficient of thermal expansion (CTE) graded layer comprising at least a dielectric portion on a first material having a first CTE to provide a first side facing said first material and a second side opposite said first side, said depositing including (i) flowing a first reactive component and at least a second reactive component, and (ii) automatically changing a gas flow ratio of said first reactive component relative to said second reactive component during a deposition time to provide a non-constant composition profile which has a graded CTE that increases from said first side to said second side, and 
   forming a metal layer comprising a second material having a second CTE on said second side, wherein said second CTE is higher than said first CTE.   
     
     
         15 . The method of  claim 14 , wherein said first material comprises said substrate and said first side contacts said substrate. 
     
     
         16 . The method of  claim 14 , wherein said CTE graded layer consists of a single phase material throughout. 
     
     
         17 . The method of  claim 15 , wherein said multi-layer structure comprises a plurality of through-substrate-vias (TSVs) that extend through said substrate from said topside to be electrically accessible from said bottomside,
 wherein said CTE graded layer comprises a CTE graded liner;   further comprising depositing a diffusion barrier metal layer directly on said second side of said CTE graded liner,   wherein said metal layer is on said diffusion barrier metal layer, and   wherein said second material comprises a metal filler on said diffusion barrier metal layer.   
     
     
         18 . The method of  claim 17 , wherein said substrate comprises silicon, wherein said TSVs comprise through-silicon-vias, and wherein said metal filler comprises copper. 
     
     
         19 . The method of  claim 14 , wherein said depositing comprises Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). 
     
     
         20 . The method of  claim 14 , wherein said automatically changing results in a varying an oxygen concentration in said CTE graded layer such that said CTE graded layer changes from silicon oxide to polysilicon during said depositing. 
     
     
         21 . The method of  claim 14 , wherein said automatically changing results in a varying a carbon concentration such that said CTE graded liner changes from silicon dioxide to a dielectric including silicon and carbon during said depositing. 
     
     
         22 . The method of  claim 14 , wherein said automatically changing comprises varying a nitrogen concentration in said CTE graded layer that results in said CTE graded liner changing from silicon dioxide to a dielectric including silicon and nitrogen during said depositing. 
     
     
         23 . The method of  claim 14 , wherein said automatically changing comprises utilizing at least one programmable mass flow controller that has a programmable time varying gas flow feature.