Intelligent architecture creator

Abstract

Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

What is claimed is: 
     
         1 . A method to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code, the IC having at least one or more timing and hardware constraints, comprising:
 a. extracting parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code;   b. iteratively optimizing the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met and using a compiler to compile, assemble and link code for each processor architecture iteration to arrive at a customized architecture; and   c. synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.   
     
     
         2 . The method of  claim 1 , comprising optimizing processor scalarity and instruction grouping rules 
     
     
         3 . The method of  claim 1 , comprising optimizing the number of processor cores needed and automatically splitting an instruction stream to use the processor cores effectively. 
     
     
         4 . The method of  claim 1 , wherein the processor architecture optimization comprises changing an instruction set, including reducing the number of instructions required and encoding the instructions to improve instruction access and decode speed, and to improve instruction memory size requirement. 
     
     
         5 . The method of  claim 1 , wherein the processor architecture optimization comprises changing one of: a register file port, port width, and number of ports to data memory. 
     
     
         6 . The method of  claim 1 , wherein the processor architecture optimization comprises changing one of: data memory size, data cache pre-fetch policy, data cache policy instruction memory size, instruction cache pre-fetch policy, and instruction cache policy. 
     
     
         7 . The method of  claim 1 , wherein the processor architecture optimization comprises adding a co-processor. 
     
     
         8 . The method of  claim 1 , comprising pre-processing the computer readable code by:
 a. determining a memory location for each pointer variable; and   b. inserting an instrumentation for each line.   
     
     
         9 . The method of  claim 1 , comprising changing the processor instruction set by automatically generating new instructions uniquely customized to the computer readable code to improve performance of the processor architecture, further including:
 a. removing dummy assignments;   b. removing redundant loop operations;   c. identifying required memory bandwidth;   d. replacing one or more software implemented flags as one or more hardware flags; and   e. reusing expired variables.   
     
     
         10 . The method of  claim 1 , wherein extracting parameters further comprises:
 a. determining an execution cycle time for each line;   b. determining an execution clock cycle count for each line;   c. determining clock cycle count for one or more bins;   d. generating an operator statistic table;   e. generating statistics for each function; and   f. sorting lines by descending order of execution count.   
     
     
         11 . The method of  claim 1 , comprising molding commonly used instructions into one or more groups and generating a custom instruction for each group to improve performance (instruction molding). 
     
     
         12 . The method of  claim 11 , comprising checking for a molding violation in the new instruction candidate. 
     
     
         13 . The method of  claim 11 , comprising applying a cost function to select an instruction molding candidate (IMC). 
     
     
         14 . The method of  claim 11 , comprising grouping instruction molding candidates (IMCs) based on statistical dependence. 
     
     
         15 . The method of  claim 1 , comprising determining timing and area costs for the architecture parameter change. 
     
     
         16 . The method of  claim 1 , comprising identifying sequences in the program to be replaced with by one or more instruction molding candidates (IMCs) and rearranging instructions within a sequence to maximize IMC usage while retaining code functionality. 
     
     
         17 . The method of  claim 1 , comprising passing information regarding candidate code to use a newly synthesized instruction to a compiler. 
     
     
         18 . The method of  claim 1 , comprising tracking pointer marching and building statistics regarding stride and memory access patterns and memory dependency to optimize cache pre-fetching and a cache policy. 
     
     
         19 . A system to automatically generate a custom integrated circuit (IC) described by a computer readable code or model, the IC having at least a floating point parameter, a performance constraint, and a static range and a dynamic range for an input signal, comprising:
 a. means for extracting parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code;   b. means for iteratively optimizing the processor architecture by changing one or more parameters to meet all timing and hardware constraints; and   c. means for synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.   
     
     
         20 . The system of  claim 19 , comprising
 a. means for molding commonly used instructions into one or more groups and generating a custom instruction for each group to improve performance (instruction molding);   b. means for checking for a molding violation in the new instruction candidate;   c. means for applying a cost function to select an instruction molding candidate (IMC) and means for grouping IMCs based on statistical dependence.