Semiconductor device having hierarchical bit line structure

Abstract

A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line.

What is claimed is: 
     
         1 . A method comprising:
 accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line;   transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and   restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line.   
     
     
         2 . The method as claimed in  claim 1 , further comprising restoring, in response to the data read mode, the data into the memory cell through the global and local bit lines. 
     
     
         3 . The method as claimed in  claim 2 , wherein the restoring responsive to the data read mode is carried out by a global sense amplifier connected to the global bit line and the restoring responsive to the refresh mode is carried out a restoring circuit connected to the local bit line. 
     
     
         4 . A method comprising:
 accessing a plurality of memory cells to all the memory cells to output data stored therein onto a plurality of local bit lines, respectively; and   performing, in response to a data read mode, a data read operation that comprises:
 designating one of the local bit lines as a selected local bit line and remaining one of the local bit lines respectively as non-selected local bit lines; 
 transferring a data signal on the selected local bit line to a global bit line; 
 restoring the data into the memory cell connected to the selected bit line through the global bit line and the selected bit line; and 
 restoring the data into the memory cells connected respectively to the non-selected local bit lines while keeping each of the non-selected local bit lines electrically isolated from the global bit line. 
   
     
     
         5 . The method as claimed in  claim 4 , wherein the restoring the data into the memory cell connected into the selected bit line through the global bit line and the selected bit line is carried out by a global sense amplifier connected to the global bit line, and the restoring the data into the memory cells connected respectively to the non-selected bit lines is carried by restoring circuits connected respectively to the local bit lines. 
     
     
         6 . A method comprising:
 accessing a plurality of memory cells to all the memory cells to output data stored therein onto a plurality of local bit lines, respectively;   performing, in response to a data read mode, a data read operation that comprises:
 designating one of the local bit lines as a selected local bit line and remaining one of the local bit lines respectively as non-selected local bit lines; 
 transferring a data signal on the selected local bit line to a global bit line; 
 restoring the data into the memory cell connected to the selected local bit line through the global bit line and the selected local bit line; and 
 restoring the data into the memory cells connected respectively to the non-selected local bit lines while keeping each of the non-selected local bit lines electrically isolated from the global bit line, and 
   performing, in response to a refresh mode, a refresh operation that comprises:
 restoring the data into the memory cells connected respectively to the local bit lines while keeping each of the local bit lines electrically isolated from the global bit line. 
   
     
     
         7 . The method as claimed in  claim 6 , wherein:
 the restoring the data into the memory cell connected to the selected local bit line through the global bit line and the selected local bit line including activating a global sense amplifier connected to the global bit line;   the restoring the data into the memory cells connected respectively to the non-selected local bit lines includes activating restoring circuits connected respectively to the non-selected local bit lines; and   the restoring the data into the memory cells connected respectively to the local bit lines includes activating each of the restoring circuits connected an associated one of the local bit lines.