Apparatus and method for efficiently executing boolean functions

Abstract

An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

What is claimed is: 
     
         1 . A processor comprising:
 a set of registers for storing packed operands;   Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the source operands,   wherein the Boolean operation comprises:   combining a bit read from each of the source operands to form an index to the immediate value, the index identifying a bit position within the immediate value;   reading the bit from the identified bit position of the immediate value; and   storing the bit from the identified bit position of the immediate value in a destination register.   
     
     
         2 . The processor as in  claim 1  wherein each bit read from the immediate value is stored in the destination register at a bit position corresponding to a bit position of the bits used to form the index from at least one of the source operands. 
     
     
         3 . The processor as in  claim 1  wherein the operations of combining, reading, and storing by the Boolean operation are performed N times using N bits read from each of the source operands to generate an N-bit result in the destination register. 
     
     
         4 . The processor as in  claim 1  wherein each of the packed operands comprises an 8-bit, 16-bit, or 32-bit operand. 
     
     
         5 . The processor as in  claim 4  wherein the register set comprises 64-bit registers. 
     
     
         6 . The processor as in  claim 1  wherein the immediate value is a byte in length and wherein the single instruction uses three source operands. 
     
     
         7 . The processor as in  claim 1  wherein the immediate value is 16-bits in length and wherein the single instruction uses four source operands. 
     
     
         8 . The processor as in  claim 1  wherein the immediate value comprises a truth table defining a bitwise logical operation to perform on the source operands. 
     
     
         9 . The processor as in  claim 8  wherein the immediate value defines a majority (MAJ) operation to be performed on the source operands. 
     
     
         10 . The processor as in  claim 8  wherein the immediate value defines a choose (CH) operation to be performed on the source operands. 
     
     
         11 . The processor as in  claim 8  wherein the immediate value defines a parity (PAR) operation to be performed on the source operands. 
     
     
         12 . The processor as in  claim 1  further comprising:
 an instruction processing pipeline which does not natively support instructions using three or more source operands. 
 
     
     
         13 . A method comprising:
 executing a single instruction which uses three or more source operands packed in a set of registers,   responsively reading at least one bit from the three source operands and an immediate value to perform a Boolean operation on the three source operands,   wherein the Boolean operation comprises:   combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value;   reading the bit from the identified bit position of the immediate value; and   storing the bit from the identified bit position of the immediate value in a destination register.   
     
     
         14 . The method as in  claim 13  wherein each bit read from the immediate value is stored in the destination register at a bit position corresponding to a bit position from which each of the bits used to form the index are read from the three or more source operands. 
     
     
         15 . The method as in  claim 13  wherein the operations of combining, reading, and storing by the Boolean operation are performed N times using N bits read from each of the source operands to generate an N-bit result in the destination register. 
     
     
         16 . The method as in  claim 13  wherein each of the packed operands comprises an 8-bit, 16-bit, or 32-bit operand. 
     
     
         17 . The method as in  claim 16  wherein the register set comprises 64-bit registers. 
     
     
         18 . The method as in  claim 13  wherein the immediate value is a byte in length and wherein the single instruction uses three source operands. 
     
     
         19 . The method as in  claim 13  wherein the immediate value is 16-bits in length and wherein the single instruction uses four source operands. 
     
     
         20 . The method as in  claim 13  wherein the immediate value comprises a truth table defining a bitwise logical operation to perform on the source operands. 
     
     
         21 . The method as in  claim 20  wherein the immediate value defines a majority (MAJ) operation to be performed on the source operands. 
     
     
         22 . The method as in  claim 20  wherein the immediate value defines a choose (CH) operation to be performed on the source operands. 
     
     
         23 . The method as in  claim 20  wherein the immediate value defines a parity (PAR) operation to be performed on the source operands.