Packet processors and packet filter processes, circuits, devices, and systems

Abstract

A packet filter ( 2500 ) for incoming communications packets includes extractor circuitry ( 2510 ) operable to extract data from a packet, and packet processor circuitry ( 2520 ) operable to concurrently mask ( 3010 ) the packet data from the extractor circuitry ( 2510 ), perform an arithmetic/logic operation ( 3020 ) on the packet to supply a packet drop signal (DROP), and perform a conditional limit operation and a conditional jump operation ( 3030 ).

What is claimed is: 
     
         1 . A processor instruction having:
 an operand field;   an arithmetic/logic field; and   a field selectively operable as a rate limit field, a jump field, and a save field.   
     
     
         2 . The processor instruction claimed in  claim 1  wherein said operand field has 1) a base register subfield that points to a location of a header location value and 2) an offset subfield representing an offset from the header location value. 
     
     
         3 . The processor instruction claimed in  claim 2  wherein said operand field further has 3) a mask subfield representing a mask for data at the offset. 
     
     
         4 . The processor instruction claimed in  claim 3  wherein said mask subfield represents a coded mask bits and said instruction further has 4) a second mask subfield representing immediate mask bits, and said coded mask bits and said immediate mask bits are concurrently-active representations. 
     
     
         5 . A process of manufacturing a mobile phone with a flash memory coupled to a processor and for packet filtering, the process comprising programming the flash memory with code representing a method of operation by the processor to configure the packet filtering based on a packet rate limit value. 
     
     
         6 . The process of manufacturing claimed in  claim 5  further comprising programming a rate limit clock pre-scaling value into the flash. 
     
     
         7 . The process of manufacturing claimed in  claim 5  wherein the packet filtering has an event logger and the process of manufacturing further comprises programming the flash with further code representing an iterative adjustment of a value representing a packet rate limit in response to packet drop information from the event logger. 
     
     
         8 . The process of manufacturing claimed in  claim 5  for a host to control a packet filter having an event logger and packet filter registers, the process of manufacturing further comprises programming the flash memory with code representing initialization by storing logging thresholds in at least one of the packet filter registers, and loading at least one packet filter register to associate drop codes indicative of different tests on packets, with the logging thresholds. 
     
     
         9 . The process of manufacturing claimed in  claim 5  further comprising programming the flash memory with the code in encrypted, signed form. 
     
     
         10 . A mobile phone comprising:
 a wireless modem for receiving packets;   a storage space for holding information from received packets;   a processor coupled to said storage space, said processor operable to produce a voice communication from the information from received packets held in said storage space; and   packet processing circuitry fed by said wireless modem and operable to drop packets that fail predetermined tests and to couple information to said storage space from received packets that do not fail the predetermined tests.   
     
     
         11 . The mobile phone claimed in  claim 10  wherein said tests include a first test for a defective packet and a second test for an excessive packet rate.