Trench gate metal oxide semiconductor field effect transistor and fabricating method thereof

Abstract

A trench gate metal oxide semiconductor field effect transistor includes a substrate and a gate. The substrate has a trench. The trench is extended downwardly from a surface of the substrate. The gate includes an insertion portion and a symmetrical protrusion portion. The insertion portion is embedded in the trench. The symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.

1 . A trench gate metal oxide semiconductor field effect transistor, comprising:
 a substrate having a trench formed therein, wherein the trench is extended downwardly from a surface of the substrate; and   a gate comprising an insertion portion and a symmetrical protrusion portion, wherein the insertion portion is embedded in the trench, and the symmetrical protrusion portion is symmetrically protruded over the surface of the substrate.   
     
     
         2 . The trench gate metal oxide semiconductor field effect transistor according to  claim 1 , wherein the symmetrical protrusion portion is wider than the trench. 
     
     
         3 . The trench gate metal oxide semiconductor field effect transistor according to  claim 1 , wherein the gate is a T-shaped gate, which is symmetrical with respect to a central line of the trench. 
     
     
         4 . The trench gate metal oxide semiconductor field effect transistor according to  claim 1 , wherein the trench has a width smaller than or equal to 0.8 μm and a depth of about 1.6 μm. 
     
     
         5 . The trench gate metal oxide semiconductor field effect transistor according to  claim 1 , further comprising:
 a dielectric material layer disposed over the surface of the substrate and the gate; and   at least one contact plug penetrated through the dielectric material layer and electrically contacted with the symmetrical protrusion portion of the gate.   
     
     
         6 . The trench gate metal oxide semiconductor field effect transistor according to  claim 1 , further comprising:
 a first-conductive doped region formed in the substrate;   a second-conductive doped region formed in the substrate, wherein a P/N junction is formed between the first-conductive doped region and the second-conductive doped region, the trench is extended downwardly from the surface of the trench, penetrated through the first-conductive doped region and the P/N junction, and inserted into the second-conductive doped region;   a gate dielectric layer formed on a sidewall of the trench; and   a source region formed in the substrate and located beside the gate dielectric layer.   
     
     
         7 . The trench gate metal oxide semiconductor field effect transistor according to  claim 6 , wherein the first-conductive doped region is a P-type body region, and the second-conductive doped region is an N-type well region. 
     
     
         8 . The trench gate metal oxide semiconductor field effect transistor according to  claim 6 , further comprising an N-type buried layer, which is disposed under the second-conductive doped region. 
     
     
         9 . The trench gate metal oxide semiconductor field effect transistor according to  claim 6 , wherein the source region is an N-type well region, and the source region is extended from the surface of the substrate into the first-conductive doped region. 
     
     
         10 . A method for fabricating a trench gate metal oxide semiconductor field effect transistor, the method comprising steps of:
 providing a substrate;   forming a hard mask layer on the substrate;   performing an etching process to remove a part of the hard mask layer and forming a trench in the substrate;   performing an etching back process to remove a part of the hard mask layer;   forming a conductive layer on the hard mask layer, and filling the polysilicon layer into the trench; and   performing a planarization process to remove the conductive layer by using the hard mask layer as a stop layer.   
     
     
         11 . The method according to  claim 10 , wherein before the hard mask layer is formed, the method further comprises a step of forming a pad silicon oxide layer on the substrate. 
     
     
         12 . The method according to  claim 10 , wherein after the hard mask layer is formed, the method further comprises a step of forming a sacrificial layer on the hard mask layer. 
     
     
         13 . The method according to  claim 10 , wherein before the conductive layer is formed, the method further comprises a step of forming a gate dielectric layer on a sidewall of the trench by a thermal oxidation process. 
     
     
         14 . The method according to  claim 10 , wherein the hard mask layer is a silicon oxide layer or a silicon nitride layer.